library IEEE;
use IEEE.std_logic_1164.all;    -- Here is defined the std_logic type 
use IEEE.std_logic_arith.all;   -- This package is needed for type conversions                                        
use WORK.all;
use WORK.LMS_pkg4.all;
use STD.TEXTIO.all;

entity LMS6test is
end LMS6test;

architecture LMS6testarq of LMS6test is

  component LMS6
    port (in_sig,sen_in,cos_in : in external_vector; 
    hab_ext,clock,reset        : in std_logic;
    lms_out                    : out external_vector;
    ending                     : out std_logic); 
  end component;

  file file_noise    : text is in "noise12.dat";
  file file_filtered : text is out "filtered12.dat";

  signal input_signal: external_vector; 
  signal sen_signal  : external_vector;
  signal cos_signal  : external_vector;
  signal out_signal  : external_vector; 
  signal relojj      : std_logic := '0';
  signal resett      : std_logic := '0';
  signal habi_ext    : std_logic := '0';
  signal fin_cal     : std_logic;

   begin

    C6 : LMS6
      port map(input_signal,sen_signal,cos_signal,habi_ext,relojj,resett,out_signal,fin_cal);            

    RELOJ : process
      begin
        relojj <= not relojj;
        wait for 50 ns;
    end process;

    RESET : process
      begin
        resett <= '0';
        wait for 80 ns;     --  reset no coincidente con el reloj
        resett <= '1';
	wait;
    end process;

    NEWDATA : process
      begin
	habi_ext <= '0';    --  otra forma de implementar un reloj de 830 ns de periodo
	wait for 215 ns;
        habi_ext <= '1';
        wait for 615 ns;
      end process;

    MAIN : process

     variable noise,sinus,cosinus : integer;
     variable filtered : integer;
     variable linea1,linea2: LINE;
      
      begin
        while not ENDFILE(file_noise) loop
            READLINE(file_noise,linea1);          
            READ(linea1,noise);
            READ(linea1,sinus);
            READ(linea1,cosinus);
            input_signal <= conv_std_logic_vector(noise,external_length);
            sen_signal <= conv_std_logic_vector(sinus,external_length);
            cos_signal <= conv_std_logic_vector(cosinus,external_length);
            wait until fin_cal'event and fin_cal='1';
            filtered := conv_integer(signed(out_signal));
            WRITE(linea2,filtered);
            WRITELINE(file_filtered,linea2);
        end loop;
        wait;
    end process;

end LMS6testarq;