Copyright: Copyright © 1998 Vantis Corporation. All Rights Reserved.
Citation: Copyright © 1998 Vantis Corporation. All Rights Reserved.


@Ifdef and Device Kit Macros Example

For example, in an ABEL-HDL source file you can enter

@ifdef _LCA_
   {
   < LCA-specific ABEL-HDL description>
   }
@ifdef _MACH_
   {
   < MACH-specific ABEL-HDL description >
   }

If you target your design to a device in the LCA device kit, the LCA-specific ABEL-HDL description is used.  If you target a MACH device, the MACH-specific description is used.  The Device Kits pass the macros to the ABEL-HDL compiler when it is run.


Hierarchy

You use hierarchy declarations in an upper-level ABEL-HDL source to refer to (instantiate) another ABEL-HDL source.  To instantiate an ABEL-HDL source file, do the following:

In the lower-level source: (optional)

Identify lower-level I/O Ports (signals) with an Interface  statement

In the top-level source

1	Declare the lower-level source with an Interface declaration

2	Instantiate the lower-level source with Functional_block  declarations.

Note:  Hierarchy declarations are not required when instantiating an ABEL-HDL source in a schematic. For instructions on instantiating lower-level source in schematics, refer to your schematic reference.

To identify I/O ports in the lower-level source

You identify ABEL-HDL source input and output ports with an Interface declaration directly following the Module statement. The Interface statement defines the ports in the lower-level source that are used by the top-level source.

You must declare all input pins in the ABEL-HDL source as ports.  You can optionally specify default values of 0, 1, or Don't-care.

You do not have to declare all output pins as ports.  Any undeclared outputs become No Connects or redundant nodes.  Redundant nodes can later be removed from the designs during post-link optimization.

The following source fragment is an example of a lower-level interface statement.

module lower
interface (a=0, [d3..d0]=7 -> [z0..z7]) ;
title 'example of lower-level interface statement ' ...

This statement identifies input a, d3, d2, d1 and d0 with default values, and outputs z0 through z7.  For more information, see Interface (lower-level source).

To specify signal attributes

Attributes specified for pins in a lower-level source are propagated up to the higher-level source.  For example, a lower-level pin with an 'invert' attribute affects the higher-level signal wired to that pin, its preset, reset, pre-load, and power-up value.

Output Enables (OE)

Connecting a lower-level tristate output to a higher-level pin results in the output enable being specified for the higher-level pin.  If another OE is specified for the higher-level pin, it is flagged as an error.  Since most tristate outputs are used as bidirectionals, it might be important to keep the lower-level OE.

Buried Nodes

Buried nodes in lower-level sources are handled as follows:

Dangling	Lower-level nodes that do not fanout are propagated to the higher-level source and become dangling nodes. Optimization may remove dangling nodes from the lower-level source.

Combinational	Combinational nodes in a lower-level source become collapsible nodes in the higher-level source.

Registered	Registered nodes are preserved with hierarchical names assigned to them.

Declaring Lower-level Source in the Top-level Source

To declare a lower-level source, you match the lower-level source interface statement with an interface declaration.  For example, to declare the lower-level source fragment given above, you would add the following declaration to your upper-level source declarations:

lower interface (a=0, [d3..d0]=7 -> [z0..z7]) ;

You could specify different default values if you want to override the ones given in the instantiated source, but otherwise it must match the lower-level interface statement exactly.  See Interface (higher-level source) for more information.

Instantiating Lower-level Source in the Top-level Source

You use a functional_block declaration in an top-level ABEL-HDL source to instantiate a declared lower-level source and make the ports of the lower-level source accessible in the upper-level source.  You must declare sources with an interface declaration before you instantiate them.

To instantiate the source declared above, add an interface declaration and signal declarations to your top-level declarations, and port connection equations to your top-level equations as shown in the source fragment below:

DECLARATIONS
   low1 FUNCTIONAL_BLOCK lower ;
   zed0..zed7 pin ; "upper-level outputs
   atop pin       ; "upper-level input
   d3..d0 pin     ; "upper-level inputs

 EQUATIONS
   low1.a = atop;                "wire this source's inputs
   low1.[d3..d0] = [d3..d0] ;    "  to lower-level inputs
   [zed0..zed7] = low1.[z0..z7]; "wire this source's outputs to
                                 "  lower-level outputs

See Also

Hierarchy and Retargeting and Fitting

Hierarchy and Test Vectors (PLD JEDEC Simulation)

Node Collapsing

Functional_block


Hierarchy and Retargeting and Fitting
Hierarchy and Retargeting

Redundant Nodes

When you link multiple sources, some redundant nodes may be generated.  These nodes usually originate from lower-level outputs that are not being used in the top-level source.  For example, when you use a 4-bit counter as a 3-bit counter.  The most significant bit of the counter is unused and can be removed from the design to save device resources.

Merging Feedbacks

Linking multiple modules can produce signals with one or more feedback types, such as .FB and .Q.  You can tell the optimizer to combine these feedbacks to help the fitting process.

Post-linked Optimization

If your design has a constant tied to an input, you can re-optimize the design.  Re-optimizing may further reduce the product terms count.For example, if you have the equation

out = i0 & i1 || !i0 & i2;

and i0 is tied to 1, the resulting equation would be simplified to

out = i1;

See Also

Hierarchy and Test Vectors (PLD JEDEC Simulation)

Node Collapsing

Building a Top-level ABEL-HDL Source

Building a Lower-level ABEL-HDL Source


Hierarchy and Test Vectors (PLD JEDEC Simulation)

If you are targeting a PLD device and want to do JEDEC simulation of your project, you must specify your test vectors in the top-level source.  If you have existing test vectors in lower-level sources, you can merge the inputs stimulus of blocks that are connected to the top-level pins with the expected values of blocks that are connected to the top-level outputs.  The test vectors in the lower-level modules can still be used for individual JEDEC simulation.

See Also

Hierarchy and Retargeting and Fitting

Node Collapsing


Node Collapsing

All combinational nodes by default are collapsible.  Nodes to be collapsed (or to be preserved) are flagged through the use of signal attributes in the language.  The attributes are:

Istype 'keep' - Do not collapse this node.

Istype 'collapse' - Collapse this node.

Collapsing provides multi-level optimization for combinational logic.  Designs with arithmetic and comparator circuits generally generate large number of product terms which will not fit to any programmable logic device.  Node collapsing allows you to describe equations in terms of multi-level combinational nodes, then collapse the nodes into the output until it reaches the product term you specify.  The result is an equation that is optimized to fit the device constraints.

Selective Collapsing

In some instances, you may want to keep certain nodes from being collapsed out.  For example, some nodes may help in the simulation process.  You can specify the nodes you do not want collapsed as Istype 'keep' and the optimizer does not collapse them.

See Also

Hierarchy and Retargeting and Fitting

Hierarchy and Test Vectors (PLD JEDEC Simulation)


Building a Top-level ABEL-HDL Source

A top-level ABEL-HDL source is built using Interface and Functional_block statements.  You must use these statements to instantiate (reference) lower-level sources.

See Also

Interface (top module)

Building a Lower-level ABEL-HDL Source


Building a Lower-level ABEL-HDL Source

A lower-level ABEL-HDL source is built using an Interface statement that provides information for the top-level source it is referenced.  Lower-level ABEL-HDL source need to contain an interface statement, even if the top-level source is a schematic.

See Also

Interface (submodule)

Building a Top-level ABEL-HDL Source


Feedback Normalization

Feedback normalization is the term used to describe the conversion of feedbacks to a standard polarity.  The standard most often used is the polarity observed on the device output pin.  Since feedbacks (both registered and combinational) can originate from a wide variety of macrocell locations, it is important to normalize feedbacks so that the same design description can be mapped to a wide variety of devices.

Register feedback is normalized to one of two locations in a device.  When a feedback is specified as .FB, or with no dot extension, the signal fed back to the array is normalized to the output pin, regardless of the actual source of the feedback.  When register feedback is specified with .Q, the signal fed back to the array is normalized to the Q output of the associated flip-flop — again regardless of the actual source of the feedback.

See Also

Feedback .Q and FB

Feedback without Dot Extensions

Device Fitters and Register Feedback

State Diagram Feedback in Equations


Device Fitters and Register Feedback

There are cases where even a fully-specified feedback can be implemented differently in different devices.  For example, the global macrocells of the E1800 feature multiple feedback paths.

To map an equation that uses .FB for feedback, the device fitter and the Fuseasm fuse mapper have two paths to choose from.  If the feedback needs to be global (distributed outside of the local quadrant of the device) then the pin feedback must be used in place of the register feedback.  To accommodate situations like this, all Data I/O fitters and the Fuseasm program use the following set of rules when interpreting .FB and .Q feedback specifications:

If the device has a direct register feedback path, then use the register feedback path:

If the feedback was specified with .FB, then normalize the polarity to the device output pin.

If the feedback was specified with .Q, then normalize the polarity to the Q output of the associated flip-flop.

If there is no direct register feedback path available, then use the pin feedback path, and ensure that the output enable (if any) is permanently enabled:

If conflicting output enable logic was specified in the design, then report an error.

If the device has a pin-controlled output enable, then report a warning error to remind the user to tie the enable pin to the appropriate enabling value.

If the feedback was specified with .FB, then normalize polarity to the output pin.

If the feedback was specified with .Q, then normalize the polarity to the Q output of the associated flip-flop.

See Also

Feedback - .Q and .FB

Feedback Without Dot Extensions

Feedback Normalization

State Diagram Feedback in Equations


State Diagram Feedback in Equations

When you write equations not directly associated with the state diagram (in a separate equations section, for example) and want to decode the current state, you can use either .FB or .Q to refer to the fed-back state register values.

Using .FB is the simplest way to refer to feedback state register values.  If you use .Q, you must consider whether 'invert' or 'buffer' was specified for the state registers, and invert the feedback signal accordingly.

Note: If you specify both .Q and .FB, the dot extensions are merged during compilation.

See Also

Feedback - .Q and .FB

Feedback Without Dot Extensions

Feedback Normalization

Device Fitters and Register Feedback


Pin-to-pin vs. Detailed Descriptions for Registered Designs

ABEL-HDL assignment operators can be used when writing high-level equations. The = operator specifies a combinational assignment, where the design is written with only the circuit's inputs and outputs in mind.  The := operator specifies a registered assignment, where you must consider the internal circuit elements (such as output inverters, presets and resets) related to the memory elements (typically flip-flops). The semantics of these two assignment operators is discussed below.

Using := for Pin-to-pin Descriptions

The := implies a memory element is associated with the output defined by the equation. For example, the equation

Q1 := !Q1 # Preset;

implies that Q1 will hold its current value until the memory element associated with that signal is clocked (or unlatched, depending on the register type).

This equation is a pin-to-pin description of the output signal Q1.  The equation describes the signal's behavior in terms of desired output pin values for various input conditions. Pin-to-pin descriptions are useful when describing a circuit that is completely architecture-independent.

Language elements that are useful for pin-to-pin descriptions are the := operator, and the .CLK, .OE, .FB, .CLR, .ACLR, .SET, .ASET and .COM dot extensions. These dot extensions help to resolve circuit ambiguities when describing architecture-independent circuits.

Pin-to-pin Descriptions

A pin-to-pin description of a device-based circuit is a description that refers only to the relationship between the device's input pins and corresponding values observed on the output pins.  Pin-to-pin descriptions do not include information about macrocell configurations, flip-flop types, or the precise form of the logic programmed into the device.

The pin-to-pin example contains a complete pin-to-pin specification of a simple 2-bit counter with a reset.

Detailed Descriptions

Pin-to-pin designs are easier to move to alternative device types, and are easier to comprehend.  However, detailed designs using ABEL dot extensions are often required to describe complex or device-specific features in a circuit.  These device features are usually associated with flip-flops and cannot be described using pin-to-pin design descriptions.

The detailed example contains the same design as the example above, except using detailed methods to take advantage of devices that have a built-in register reset.

Mixed Descriptions

You can mix pin-to-pin and detailed description methods in the same design.  The mixed example contains a source file where only the reset function is described using detailed design methods; the rest of the circuit is described pin-to-pin.

See Also

Resolving Feedback Ambiguities

Detailed Circuit Descriptions

Designing for Macrocells

Examples of Pin-to-Pin and Detailed Descriptions


Pin-to-Pin Example

This example is a pin-to-pin description of a 2-bit counter with a reset.

module count
   q0,q1 pin istype 'reg';
   clock pin;
   reset pin;
equations
   [q1,q0].clk = clock;
   [q1,q0] := ([q1.fb,q0.fb] + 1) & !reset;
test vectors ([clock,reset]->[q1,q0])
        [ .c.  , 1 ]->[ 0, 0];
        [ .c.  , 0 ]->[ 0, 1];
        [ .c.  , 0 ]->[ 1, 0];
        [ .c.  , 0 ]->[ 1, 1];
        [ .c.  , 0 ]->[ 0, 0];
        [ .c.  , 0 ]->[ 0, 1];
        [ .c.  , 1 ]->[ 0, 0];
end


Detailed Example

This example describes a 2-bit counter that uses the built-in register reset of some devices.

module count
   q0,q1 pin istype 'reg,buffer';
   clock pin;
   reset pin ;
equations
   [q1,q0].clk = clock;
   [q1.D,q0.D] = [q1.Q,q0.Q] + 1;
   [q1.SR,q0.SR] = reset;
test vectors  ([clock,reset]->[q1,q0])
        [ .c.  , 1 ]->[ 0, 0];
            :
end

Pin-to-pin design methods cannot be used for this form of the design, since there is no pin-to-pin syntax for describing reset logic for built-in reset features.  This design uses an istype 'buffer' declaration to ensure that the flip-flop reset propagates to the pin without an unwanted inversion.

Note: When you describe a preset or reset function with a detailed description, you need to include an 'invert' or 'buffer' attribute.  If you specify 'invert', the preset logic is reversed (and acts as a reset when observed from the pin).


Mixed Pin-to-pin and Detailed Example

In this example, pin-to-pin and detailed descriptions are combined: the reset function is described using detailed design methods, and the rest of the circuit is described pin-to-pin.

module count
   q0,q1 pin istype 'reg,buffer';
   clock pin;
   reset pin;
equations
   [q1,q0].clk = clock;
   [q1,q0] := [q1.FB,q0.FB] + 1;
   [q1.SR,q0.SR] = reset;
test vectors ([clock,reset]->[q1,q0])
       [ .c.  , 1 ]->[ 0, 0];
           :
end

Note: When you describe a preset or reset function with a detailed description, you need to include an 'invert' or 'buffer' attribute.  If you specify 'invert', the preset logic is reversed (and acts as a reset when observed from the pin).


Feedback Specification - .Q and .FB

The .Q and .FB dot extensions both specify that the associated flip-flop is the source of the feedback signal, but the polarity of the resulting feedback signal may differ depending on the macrocell configuration.  The figure below demonstrates the difference.

The first macrocell has an inverted output pin, but the second macrocell has a non-inverted output pin.  The output inversion in the first diagram corresponds to the istype 'invert' attribute in ABEL-HDL.  The second diagram corresponds to istype 'buffer'.  In the inverted diagram, the .Q feedback dot extension is the complement of the .FB dot extension; while in the non-inverted diagram, the two dot extensions are identical.

In the above figure, the feedback path is shown as though it originated at the Q output of the flip-flop.  In actuality, the feedback usually originates at the Q-bar output of the flip-flop, but the result is the same: the feedback paths are adjusted automatically to reflect the actual source of the signal:

See Also

Feedback Without Dot Extensions

Feedback Normalization

Device Fitters and Register Feedback

State Diagram Feedback in Equations

Istypes


Feedbacks Specified Without Dot Extensions

When a registered signal is specified with no feedback dot extension as a reference, the results depend on the type of device that is selected for fitting.  If the device selected has multiple feedback paths (for example, registered and combinational, or register and pin) then the feedback is ambiguous, and the results can be difficult to determine.

For example, consider the following simple counter design.

module count
    q0,q1 pin istype 'reg';
    clock pin;
    reset pin;
equations
    [q1,q0].clk = clock;
    [q1,q0]    := ([q1,q0] + 1) & !reset;

test_vectors
        ([clock,reset]->[q1,q0])
         [ .c.  , 1 ]->[ 0, 0];
         [ .c.  , 0 ]->[ 0, 1];
         [ .c.  , 0 ]->[ 1, 0];
         [ .c.  , 0 ]->[ 1, 1];
         [ .c.  , 0 ]->[ 0, 0];
         [ .c.  , 0 ]->[ 0, 1];
         [ .c.  , 1 ]->[ 0, 0];
end

Since the q0 and q1 signals have not been referenced in the equations with feedback dot extensions, the operation of the circuit can differ depending on the device selected.  The Equation Simulator and all Device Kit fitters created by Data I/O follow the same feedback rules when mapping unspecified feedbacks to devices.

See Also

Feedback - .Q and .FB

Feedback Normalization

Device Fitters and Register Feedback

State Diagram Feedback in Equations


Feedback Rules

The Fitters use the following feedback rules:

If the device specified has a pin feedback path, use the pin feedback.

If there is no pin feedback path, and the device has a register feedback path, use the register feedback path and normalize the feedback signal to the pin.

Do not consider the state of the output enables (in either case).

Following these rules, the counter design presented earlier would operate incorrectly if implemented in a device with a pin feedback path, since no output enable logic was specified.  In devices with multiple feedback paths, the pin feedback takes precedence over the register feedback path when no dot extension is specified.

See Also

Feedback - .Q and .FB

Feedback Without Dot

Feedback Normalization

Device Fitters and Register Feedback

State Diagram Feedback in Equations


Using Symbolic State Machines
Using Symbolic State Descriptions

Symbolic state descriptions describe a state machine without having to specify actual state values.  An example of a symbolic state description is shown below.

module SM
  a,b,clock         pin;                  " inputs
  a_reset,s_reset   pin;                  " reset inputs
  x,y               pin istype 'com';     " simple outputs

  sreg1             state_register;
  S0..S3            state;

equations
  sreg1.clk = clock;
state_diagram sreg1
  state S0:
      goto S1 with {x = a & b;
                    y = 0;  };

  state S1: if (a & b)
            then S2 with {x = 0;
                          y = 1; };

  state S2: x = a & b;
            y = 1;
            if (a) then S1 else S2;

  state S3:
      goto S0 with {x = 1;
                    y = 0; };

  async_reset S0: a_reset;

  sync_reset S0: s_reset;

end

Symbolic state descriptions use the same syntax as non-symbolic state descriptions; the only difference is the addition of the State_register and State declarations, and the addition of symbolic synchronous and asynchronous reset statements.

Symbolic Reset Statements

In symbolic state descriptions, the Sync_Reset and Async_Reset statements specify synchronous or asynchronous state machine reset logic.  For example, to specify that a state machine must asynchronously reset to state Start when the Reset input is true, you write

ASYNC_RESET Start : (Reset) ;

Symbolic Test Vectors

You can also write test vectors to refer to symbolic state values by entering the symbolic state register name in the test vector header (in the output sections), and the symbolic state names in the test vectors as output values.


Using Complement Arrays

The complement array is a unique feature found in some logic sequencers. This section shows a typical use in termination of a counter sequence.

Transition equations can be used to express the design of counters and state machines in some devices that contain JK or RS flip-flops.  A transition equation expresses a state of the circuit as a variation of, or an adjustment to, the previous state.  This type of equation eliminates the need to specify every node of the circuit; you can specify only those that require a transition to the opposite state.

An example of transition equations is shown in the source file below.  The source file describes a decade counter having a single (clock) input and a single latched output.  This counter divides the clock input by a factor of ten and generates a 50% duty-cycle squarewave output.  The device used for this design is an F105 FPLS.  In addition to its registered outputs, this device contains a set of "buried" (or feedback) registers whose outputs are fed back to the product term inputs. These nodes must be declared, and can be given any names.

Node 49, the complement array feedback, is declared (as COMP) so that it can be entered into each of the equations.  In this design, the complement array feedback is used to wrap the counter back around to zero from state nine, and also to reset it to zero in the event an illegal counter state is encountered. Any illegal state (and also state 9) will result the absence of an active product term to hold node 49 at a logic low.  When node 49 is low, product term 9 resets each of the feedback registers so that the counter is set to state zero.  (To simplify the following description of the equations in module decade below, node 49 and the complement array feedback are temporarily ignored.)

The first equation states that the F0 (output) register is set (to provide the counter output) and the P0 register is set when registers P0, P1, P2, and P3 are all reset (counter at state zero) and the clear input is low.  Module decade below shows how the fuses are blown to fulfill this equation; the complemented outputs of the registers (with the clear input low) form product term 0.  Product term 0 sets register P0 to increment the decade counter to state 1, and sets register F0 to provide an output at pin 18.

module DECADE
title 'Decade Counter   Uses Complement Array
Michael Holley   Data I/O Corp'

       decade          device 'F105';
       Clk,Clr,F0,PR   pin  1,8,18,19;
       P3,P2,P1,P0     node 40,39,38,37;
       COMP            node 49;
       F0,P3,P2,P1,P0  istype 'reg_sr,buffer';

        _State          = [P3,P2,P1,P0];
        H,L,Ck,X        = 1, 0, .C., .X.;

equations
    [P3,P2,P1,P0,F0].ap  = PR;
    [F0,P3,P2,P1,P0].clk = Clk;

   "Output          Next State             Present State        Input
 [F0.S, COMP,    P0.S] = !P3.Q & !P2.Q & !P1.Q & !P0.Q & !Clr; "0 to 1

 [      COMP,          P1.S,P0.R] = !P3.Q & !P2.Q & !P1.Q &  P0.Q & !Clr; "1 to 2
 [      COMP,               P0.S] = !P3.Q & !P2.Q &  P1.Q & !P0.Q & !Clr; "2 to 3
 [      COMP,     P2.S,P1.R,P0.R] = !P3.Q & !P2.Q &  P1.Q &  P0.Q & !Clr; "3 to 4
 [      COMP,               P0.S] = !P3.Q &  P2.Q & !P1.Q & !P0.Q & !Clr; "4 to 5
 [F0.R, COMP,          P1.S,P0.R] = !P3.Q &  P2.Q & !P1.Q &  P0.Q & !Clr; "5 to 6
 [      COMP,               P0.S] = !P3.Q &  P2.Q &  P1.Q & !P0.Q & !Clr; "6 to 7
 [      COMP,P3.S,P2.R,P1.R,P0.R] = !P3.Q &  P2.Q &  P1.Q &  P0.Q & !Clr; "7 to 8
 [      COMP,               P0.S] =  P3.Q & !P2.Q & !P1.Q & !P0.Q & !Clr; "8 to 9
 [           P3.R,P2.R,P1.R,P0.R] =  !COMP; "Clear

"After Preset, clocking is inhibited until High-to-Low clock transition.
test_vectors   ([Clk,PR,Clr] -> [_State,F0  ])
                [ 0 , 0, 0 ] -> [   X  , X];
                [ 1 , 1, 0 ] -> [^b1111, H]; " Preset high
                [ 1 , 0, 0 ] -> [^b1111, H]; " Preset low
                [ Ck, 0, 0 ] -> [   0  , H]; " COMP forces to State 0
                [ Ck, 0, 0 ] -> [   1  , H];
                [ Ck, 0, 0 ] -> [   2  , H];
                [ Ck, 0, 0 ] -> [   3  , H];
                [ Ck, 0, 0 ] -> [   4  , H];
                [ Ck, 0, 0 ] -> [   5  , H];
                [ Ck, 0, 0 ] -> [   6  , L];
                [ Ck, 0, 0 ] -> [   7  , L];
                [ Ck, 0, 0 ] -> [   8  , L];
                [ Ck, 0, 0 ] -> [   9  , L];
                [ Ck, 0, 0 ] -> [   0  , L];
                [ Ck, 0, 0 ] -> [   1  , H];
                [ Ck, 0, 0 ] -> [   2  , H];
                [ Ck, 0, 1 ] -> [   0  , H]; " Clear
end

The second equation performs a transition from state 1 to state 2 by setting the P1 register and resetting the P0 register.  (The .R dot extension is used to define the reset input of the registers.) In state 2, the F0 register remains set, maintaining the high output.  The third equation again sets the P0 register to achieve state 3 (P0 and P1 both set), while the fourth resets P0 and P1, and sets P2 for state 4, and so on.

Wraparound of the counter from state 9 to state 0 is achieved by means of the complement array node (node 49).  The last equation defines state 0 (P3, P2, P1, and P0 all reset) as equal to !COMP, that is, node 49 at a logic low.  When this equation is processed by ABEL, the fuses are blown (as indicated in the figure accompanying the "Using Complement Arrays" discussion in the ABEL-HDL Reference Manual).  That figure shows that state 9 (P0 and P3 set) provides no product term to pull node 49 high.  As a result, the !COMP signal is true to generate product term 9 and reset all the "buried" registers to zero.


Pin-to-Pin Language Features

You do not need to specify a device in your ABEL-HDL source file. You can also omit pin numbers from signal declarations.

When you do not specify a device or pin numbers, you need to specify pin-to-pin attributes for declared signals, since the ABEL-HDL compiler cannot imply signal attributes from predetermined device attributes. If you do not specify signal attributes or other information (such as the dot extensions, which are described later), your design might not operate consistently if you later transfer it to a different target device.

Device-independence Vs. Architecture-independence

The requirement for signal attributes does not mean that a complex design must always be specified with a particular device in mind.  You may still have to understand the differences between, for example, a P22V10 PAL and an EP600 EPLD, but you do not have to specify a particular device when describing your design.

The attributes and dot extensions provided in ABEL-HDL help you refine your design to work consistently when moving from one class of device architecture to another; for example from devices having inverted outputs to those with a particular kind of reset/preset circuitry. The more you refine your design using these language features, the more restrictive your design becomes in terms of the number of device architectures it is appropriate for.  However, by using attributes and dot extensions carefully, you can avoid specifying a particular device type, and instead target your design to a more general class of device architectures.

Signal Attributes

Signal attributes remove ambiguities that occur when no specific device architecture is declared.  If your design does not use device-related attributes (either implied by a device statement or expressed in an

ISTYPE statement), it may not operate the same way when targeted to different device architectures.  See "Pin Declaration," "Node Declaration" and "Istype" in the Chapter "Language Reference."

Signal Dot Extensions

Signal dot extensions, like attributes, are a way you can more precisely describe the behavior of a circuit that may be targeted to different architectures. Dot extensions are applied to signals, and remove the ambiguities in equations.

Refer to .ext for more information.

See Also

Pin-to-pin Vs. Detailed Descriptions for Registered Designs


Resolving Feedback Ambiguities

In the equation above (Q1 := !Q1 # Preset;), there is an ambiguous feedback condition. The signal Q1 appears on the right side of the equation, but there is no indication of whether that fed-back signal should originate at the register, should come directly from the combinational logic that forms the input to the register, or should come from the I/O pin associated with Q1. There is also no indication of what type of register should be used (although register synthesis algorithms could, theoretically, map this equation into virtually any register type). The equation could be more completely specified by writing:

Q1.CLK  =  Clock;      "Register clocked from input
Q1 := !Q1.FB # Preset; "Reg. feedback normalized to pin value

This set of equations describes the circuit completely, and specifies enough information that the circuit will operate identically in virtually any device in which it can be fit. The feedback path is specified to be from the register itself, and the .CLK equation specifies that the memory element is clocked, rather than latched.


Detailed Circuit Descriptions

In contrast to a pin-to-pin description, the same circuit can be specified in a detailed form of design description, as follows:

Q1.CLK =  Clock;            "Register clocked from input
Q1.D   =  !Q1.Q # Preset;  "D-type f/f used for register

In this form of the design, specifying the D input to a D-type flip-flop and specifying feedback directly from the register restricts the device architectures the design can be implemented in. Furthermore, the equations only describe the inputs to and feedback from the flip-flop, and do not provide any information regarding the configuration of the actual output pin. This means the design will operate quite differently when implemented in a device with inverted outputs (a simple P16R4 PAL device, for example), versus in a device with non-inverting outputs (such as an EP600).

To maintain the correct pin behavior using detailed equations, one additional language element, a 'buffer' (or its complement, 'invert') attribute, is required.  The 'buffer' attribute ensures that the final implementation in a device has no inversion between the specified D-type flip-flop and the output pin associated with Q1.  For example, add the following to the declarations section:

Q1 pin istype 'buffer';


Detailed Descriptions: Designing for Macrocells

One way to understand the difference between pin-to-pin and detailed description methods is to think of detailed descriptions as macrocell specifications.  A macrocell is a block of circuitry normally (but not always) associated with a device's I/O pin. The following diagram illustrates a typical macrocell associated with signal Q1:

Detailed descriptions are written for the various input ports (the diagram shows them with dot extension labels) of the macrocell.  Note that the macrocell shown features a configurable inversion between the Q output of the flip-flop and the output pin labeled Q1. If this inverter is used (or if a device is selected that features a fixed inversion), then the behavior seen on the Q1 output pin will be inverted from the logic applied to or observed on the various macrocell ports, including the feedback port Q1.q.

Pin-to-pin descriptions, on the other hand, allow you to describe your circuit in terms of the behavior expected on an actual output pin, regardless of the architecture of the underlying macrocell.  The following diagram illustrates the pin-to-pin concept:

When pin-to-pin descriptions are written in ABEL-HDL, the "generic macrocell" shown above is synthesized from whatever type of macrocell actually exists in the target device.


Examples of Pin-to-pin and Detailed Descriptions

Two equivalent module descriptions, one pin-to-pin and one detailed, are shown below for comparison:

Pin-to-pin Module Description

module Q1_1
  Q1              pin     istype 'reg';
  Clock,Preset    pin;

equations
  Q1.clk  =  Clock;
  Q1     := !Q1.fb # Preset;

test_vectors ([Clock,Preset] -> Q1)
              [ .c. ,   1  ] -> 1;
              [ .c. ,   0  ] -> 0;
              [ .c. ,   0  ] -> 1;
              [ .c. ,   0  ] -> 0;
              [ .c. ,   1  ] -> 1;
              [ .c. ,   1  ] -> 1;
end

Detailed Module Description

module Q1_2
  Q1              pin     istype 'reg_D,buffer';
  Clock,Preset    pin;

equations
  Q1.CLK  =  Clock;
  Q1.D    = !Q1.Q # Preset;

test_vectors ([Clock,Preset] -> Q1)
              [ .c. ,   1  ] -> 1;
              [ .c. ,   0  ] -> 0;
              [ .c. ,   0  ] -> 1;
              [ .c. ,   0  ] -> 0;
              [ .c. ,   1  ] -> 1;
              [ .c. ,   1  ] -> 1;
end

The first description can be targeted into virtually any device (if register synthesis and device fitting features are available) while the second one can be targeted only to devices featuring D-type flip-flops and non-inverting outputs.

To implement the second (detailed) module into a device with inverting outputs, the source file would need to be modified as described in Detailed Module with Inverted Outputs :

See Also

When to Use Detailed Descriptions

Using := for Alternative Flip-flop Types


Detailed Module with Inverted Outputs

module Q1_3
  Q1              pin     istype 'reg_D,invert';
  Clock,Preset    pin;

equations
  Q1.CLK  =  Clock;
 !Q1.D    =  Q1.Q # Preset;

test_vectors ([Clock,Preset] -> Q1)
              [ .c. ,   1  ] -> 1;
              [ .c. ,   0  ] -> 0;
              [ .c. ,   0  ] -> 1;
              [ .c. ,   0  ] -> 0;
              [ .c. ,   1  ] -> 1;
              [ .c. ,   1  ] -> 1;
end

In this version of the module, the existence of an inverter between the output of the D-type flip-flop and the output pin (specified with the 'invert' attribute) has necessitated a change in the equation for Q1.D.

As this example shows, using device independence and pin-to-pin description methods is desirable, since you can describe a circuit completely for any implementation.  Using pin-to-pin descriptions and generalized dot extensions (such as .FB, .CLK and .OE) as much as possible allows you to implement your ABEL-HDL module into any one of a particular class of devices. (For example, any device that features enough flip-flops and appropriately configured I/O resources.) However, the need for particular types of device features (such as register preset or reset) might limit your ability to describe your design in a completely architecture-independent way.

If, for example, a built-in register preset feature is used in a simple design, the target architectures are limited. Consider this version of the design:

module Q1_5
  Q1              pin     istype 'reg,buffer';
  Clock,Preset    pin;

equations
  Q1.CLK  =  Clock;
  Q1.AP   =  Preset;
  Q1     :=  !Q1.fb ;

test_vectors ([Clock,Preset] -> Q1)
              [ .c. ,   1  ] -> 1;
              [ .c. ,   0  ] -> 0;
              [ .c. ,   0  ] -> 1;
              [ .c. ,   0  ] -> 0;
              [ .c. ,   1  ] -> 1;
              [ .c. ,   1  ] -> 1;
end

The equation for Q1 still uses the := assignment operator and .FB for a pin-to-pin description of Q1's behavior, but the use of .AP to describe the reset function requires consideration of different device architectures. The .AP extension, like the .D and .Q extensions, is associated with a flip-flop input, not with a device output pin. If the target device has inverted outputs, the design will not reset properly, so this ambiguous reset behavior is removed by using the 'buffer' attribute, with the result of reducing the number of devices for the design to those that feature non-inverted outputs.

Using .ASET instead of .AP can solve this problem if the fitter being used supports the .ASET dot extension.

The versions 5 and 7 of the design above and below are unambiguous, but each is restricted to certain classes of devices:

module Q1_7
  Q1              pin     istype 'reg,invert';
  Clock,Preset    pin;

equations
  Q1.CLK  =  Clock;
  Q1.AR   =  Preset;
  Q1     :=  !Q1.fb ;

test_vectors ([Clock,Preset] -> Q1)
              [ .c. ,   1  ] -> 1;
              [ .c. ,   0  ] -> 0;
              [ .c. ,   0  ] -> 1;
              [ .c. ,   0  ] -> 0;
              [ .c. ,   1  ] -> 1;
              [ .c. ,   1  ] -> 1;
end


When to Use Detailed Descriptions

Although the pin-to-pin description is preferable, there are frequently situations in which more detailed descriptions must be used.  If you are unsure about which method to use for various parts of your design, examine the design's requirements. If the design uses specific features of a device (such as register preset or unusual flip-flop configurations) then detailed descriptions are probably necessary. If your design is a simple combinational function, or matches the "generic" macrocell in its requirements, then you can probably use simple pin-to-pin descriptions.


Using := for Alternative Flip-flop Types

In ABEL-HDL you can specify a variety of flip-flop types using attributes such as 'reg_D' and 'reg_JK'.  However, the use of these attributes does not enforce the use of a specific flip-flop type when a device is selected later, and does not affect the meaning of the := assignment operator. The := assignment can be thought of as a memory operator. The type of register that most closely matches the := operator's behavior is the D-type flip-flop.

The primary use for attributes such as 'reg_D', 'reg_JK' and 'reg_SR' is to control the generation of logic.  Specifying one of the 'reg_' attributes (for example, 'reg_D') instructs the ABEL-HDL compiler to generate equations using the.D extension regardless of whether the design was written using .D, := or some other method (for example, state diagrams).

Note: You need to also specify 'invert' or 'buffer' whenever using detailed syntax.

Using := for flip-flop types other than D-type is only possible if register synthesis features are available to convert the generated equations into equations appropriate for the alternative flip-flop type specified. Since the use of register synthesis to convert D-type flip-flop stimulus into JK or SR-type stimulus usually results in inefficient circuitry, the use of := for these flip-flop types is discouraged. Instead, you should use the .J and .K extensions (for JK-type flip-flops) or the .S and .R extensions (for SR-type flip-flops) and use a detailed description method (including 'invert' or 'buffer' attributes) to describe designs for these register types.

There is no provision in the language for directly writing pin-to-pin equations for registers other than D-type. State diagrams, however, may be used to describe pin-to-pin behavior for any register type.


Introduction to ABEL-HDL

ABEL-HDL is a hardware description language that supports a variety of behavioral input forms, including high-level equations, state diagrams, and truth tables.  The ABEL and DesignDirect versions of the ABEL-HDL compiler (and supporting software) functionally verify ABEL-HDL designs through simulation.  The compilers then implement the designs in PLDs or FPGAs.  ABEL-HDL designs can also be transferred to other design environments through standard-format design transfer files.

You can enter designs in ABEL-HDL and verify them with little or no concern for the architecture of the target device.

Architecture-independent design descriptions (those that do not include device declarations and pin number declarations) require more comprehensive descriptions than their architecture-specific counterparts.  Assumptions that can be made when a particular device is specified are not possible when no device is specified.  See the section Design Considerations for a more detailed discussion.


Basic Syntax

Each line in an ABEL-HDL source file must conform to the following syntax rules and restrictions:

A line can be up to 150 characters long.

Lines are ended by a line feed (hex 0A), by a vertical tab (hex 0B), or by a form feed (hex 0C).  Carriage returns in a line are ignored, so common end-of-line sequences, such as carriage return/line feed, are interpreted as line feeds.  In most cases, you can end a line by pressing  Enter.

Keywords, identifiers, and numbers must be separated by at least one space.  Exceptions to this rule are lists of identifiers separated by commas, expressions where identifiers or numbers are separated by operators, or where parentheses provide the separation.

Neither spaces nor periods can be imbedded in the middle of keywords, numbers, operators, or identifiers.  Spaces can appear in strings, comments, blocks, and actual arguments.  For example, if the keyword MODULE is entered as MOD ULE, it is interpreted as two identifiers, MOD and ULE.  Similarly, if you enter 102 05 (instead of 10205), it is interpreted as two numbers, 102 and 5.

Keywords can be uppercase, lowercase or mixed-case.

Identifiers (user-supplied names and labels) can be uppercase, lowercase or mixed-case, but are case sensitive: the identifier, output, typed in all lowercase letters, is not the same as the identifier, Output.

See Also

Supported ASCII Characters

Identifiers

Constants

Blocks

Comments

Numbers

Strings


Supported ASCII Characters

All uppercase and lowercase alphabetic characters and most other characters on common keyboards are supported. Valid characters are listed or shown below.

a - z (lowercase alphabet)
A - Z (uppercase alphabet)
0 - 9 (digits)
<space}
<tab>
!  @ # $ ? + & * ( ) -

_ = + [ ] { }  ;  : '  "

` \ | , < > .  /  ^ %


Identifiers

Identifiers are names that identify the following items:

•	devices

•	device pins or nodes

•	functional blocks

•	sets

•	input or output signals

•	constants

•	macros

•	dummy arguments

All of these items are discussed later in this chapter.  The rules and restrictions for identifiers are the same regardless of what the identifier describes.

The rules governing identifiers are listed below:

•	Identifiers can be up to 31 characters.  Longer names are flagged as an error.

•	Identifiers must begin with an alphabetic character or with an underscore.

•	Other than the first character, identifiers can contain upper- and lowercase characters, digits, tildes (~), and underscores.

•	You cannot use spaces in an identifier.  Use underscores or uppercase letters to separate words.

•	Except for Reserved Identifiers (Keywords), identifiers are case sensitive: uppercase letters and lowercase letters are not the same.

•	You cannot use periods in an identifier, except with a supported dot extension.

Some supported identifiers are listed below:

HELLO
hello
_K5input
P_h
This_is_a_long_identifier
AnotherLongIdentifier

Some unsupported identifiers are listed below:

7_      Does not begin with a letter or underscore
$4      Does not begin with a letter or underscore
HEL.LO  Contains a period (.LO is not a valid dot extension)
b6 kj   Contains a space

The last of these identifiers is interpreted as two identifiers, b6 and kj.

See Also

Reserved Identifiers (Keywords)

Choosing Identifiers


Reserved Identifiers (Keywords)

The keywords listed below are reserved identifiers.  Keywords cannot be used to name devices, pins, nodes, constants, sets, macros, or signals.  If a keyword is used in the wrong context, an error is flagged.

async_reset
case
declarations
device
else
enable (obsolete)
end
endcase
endwith
equations
external
flag (obsolete)
functional_block
fuses
goto
if
in
interface
istype
library
macro
module
node
options
pin
property
state
state_diagram
state_register
sync_reset
test_vectors
then
title
trace
truth_table
when
with


Choosing Identifiers

Choosing the right identifiers can make a source file easy to read and understand.  The following suggestions can help make your logic descriptions self-explanatory, eliminating the need for extensive documentation.

•	Choose identifiers that match their function.  For example, the pin you're going to use as the carry-in on an adder could be named Carry_In.  For a simple OR gate, the two input pins might be given the identifiers IN1 and IN2, and the output might be named OR.

•	Avoid large numbers of similar identifiers.  For example, do not name the outputs of a 16 bit adder:

ADDER_OUTPUT_BIT_1 ADDER_OUTPUT_BIT_2 and so on.

•	Use underscores or mixed-case characters to separate words in your identifier.

THIS_IS_AN_IDENTIFIER
ThisIsAnIdentifier

are much easier to read than:

THISISANIDENTIFIER


Blocks

Blocks are sections of text enclosed in braces, { and }.  Blocks are used in equations, state diagrams, macros, and directives.  The text in a block can be on one line or it can span many lines.  Some examples of blocks are shown below:{XE Blocks>

{ this is a block }
{ this is also a block, and it
spans more than one line.  }

{ A = B # C;
D = [0, 1] + [1, 0];
}

Blocks can be nested within other blocks, as shown below, where the block { D = A } is nested within a larger block:

{   A = B $ C;
  { D = A; }
    E = C;      }

Blocks and nested blocks can be useful in macros and when used with directives.  (See "Macro Declarations" later in this chapter and in <$R[C*,chlangref]Chapter 6>, "Language Reference.")

If you need a brace as a character in a block, precede it with a backslash.  For example, to specify a block containing the characters { }, write

{ \{ \} }

See Also

Using Blocks in Logic Descriptions

Using Blocks for State Diagram Transitions


Using Blocks in Logic Descriptions

Using blocks can simplify the description of output logic in equations and state diagrams and allow more-complex functions than possible without blocks.  Blocks can improve the readability of your design.

Blocks are supported anywhere a single equation is supported.  You can use blocks in simple equations, When-then-else, If-then-else, Case, and With statements

When you use equation blocks within a conditional expression (such as If-then, Case, or When-then), the logic functions are logically ANDed with the conditional expression.

See Also

Blocks in Equations

With Blocks

Blocks in State Diagrams


Blocks in Equations

The following expressions, written without blocks, are limited by the inability to specify more than one output in a When-then expression without using set notation:

Without Blocks:

WHEN        (Mode == S_Data) THEN  Out_data := S_in;
ELSE WHEN   (Mode == T_Data) THEN  Out_data := T_in;
WHEN        (Mode == S_Data) THEN  S_Valid  := 1;
ELSE WHEN   (Mode == T_Data) THEN  T_Valid  := 1;

With blocks (delimited with braces { } ), the syntax above can be simplified.  The logic specified for Out_data is logically ANDed with the WHEN clause:


With Blocks

WHEN       (Mode == S_Data) THEN { Out_data := S_in;
                                   S_Valid  := 1;  }
ELSE WHEN  (Mode == T_Data) THEN { Out_data := T_in;
                                   T_Valid  := 1;    }


Blocks in State Diagrams

Blocks also provide a simpler way to write state diagram output equations.  For example, the following two state transition statements are equivalent:

Without Blocks:

IF (Hold)  THEN State1 WITH o1 := o1.fb;  o2 := o2.fb;
ELSE State2;

With Blocks:

IF (Hold)  THEN State1 WITH {o1 := o1.fb;  o2 := o2.fb;}
ELSE State2;


Using Blocks for State Diagram Transitions

Blocks can be used to nest IF-THEN and IF-THEN-ELSE statements in state diagram descriptions, simplifying the description of complex transition logic.

See Also

Blocks for Transition Logic


Blocks for Transition Logic

Without Blocks:

IF (Hold & !Reset) THEN State1;
If (Hold & Error)  THEN State2;
If (!Hold) THEN State3;

With Blocks:

If (Hold) THEN
{   IF (!Reset) THEN State1;
    IF (Error)  THEN State2; }
ELSE State3;


Comments

Comments are another way to make a source file easy to understand.  Comments explain what is not readily apparent from the source code itself, and do not affect the code.  Comments cannot be imbedded within keywords.

You can enter comments two ways:

•	Begin with a double quotation mark (") and end with either another double quotation mark or the end of line.

•	Begin with a double forward slash (//) and end with the end of the line.  This is useful for commenting out lines of ABEL source that contain quote-delineated comments.

Examples of comments are shown in boldface below:

MODULE Basic_Logic; "gives the module a name
TITLE 'ABEL-HDL design example: simple gates'; "title

"declaration section"
IC4 device 'P10L8'; "declare IC4 to be a P10L8
IC5 "decoder PAL" device 'P10H8';

//IC5 "decoder PAL" device 'p10h8';

The information inside single quotation marks (apostrophes) are required strings, not comments, and are part of the statement.


Numbers

All numeric operations in ABEL-HDL are performed to 128-bit accuracy, which means the supported numeric values are in the range 0 to 2128 minus 1.  Numbers are represented in any of five forms.  The four most common forms represent numbers in different bases.  The fifth form uses alphabetic characters to represent a numeric value.

When one of the four bases other than the default base is chosen to represent a number, the base used is indicated by a symbol preceding the number.  The table below lists the four bases supported by ABEL-HDL and their accompanying symbols.  The base symbols can be upper- or lowercase.

Base Name	Base	Symbol
Binary	2	^b
Octal	8	^o
Decimal	10	^d (default)
Hexadecimal	16	^h

When a number is specified and is not preceded by a base symbol, it is assumed to be in the default base numbering system.  The normal default base is base 10.  Therefore, numbers are represented in decimal form unless they are preceded by a symbol indicating that another base is to be used.

You can change the default number base.  See @RADIX in <$R[C*,chlangref]Chapter 6>, "Language Reference," for more information.  Examples of supported number specifications are shown below.  The default base is base ten (decimal).

Specification	Decimal Value
75	75
^h75	117
^b101	5
^o17	15
^h0F	15
Note:  The carat (^) is a keyboard character.  It is not part of a control-key sequence.

You can also specify numbers by strings of one or more alphabetic characters, using the numeric ASCII code of the letter as the value.  For example, the character "a" is decimal 97 and hexadecimal 61 in ASCII coding.  The decimal value 97 is used if "a" is specified as a number.

Sequences of alphabetic characters are first converted to their binary ASCII values and then concatenated to form numbers.  Some examples are shown below:

Specification	Hex Value	Decimal Value
a	^h61	97
b	^h62	98
abc	^h616263	6382203


Strings

Strings are series of ASCII characters, including spaces, enclosed by apostrophes.  Strings are used in the TITLE, MODULE, and OPTIONS statements, and in pin, node, and attribute declarations, as shown below:

'Hello'
' Text with a space in front'
' '
'The preceding line is an empty string'
'Punctuation? is allowed !!'

You can include a single quote in a string by preceding the quote with a backslash, (\).

'It\'s easy to use ABEL and DesignDirect'

You can include backslashes in a string by using two of them in succession.

'He\\she can use backslashes in a string'

Note:  The grave accent (`) is also accepted as a string delimiter and can be used interchangeably with the apostrophe (').


Directives
@directive - Directives

Purpose	Directives affect the contents of a source file when it is processed.  Sections of ABEL-HDL source code can be included conditionally, code can be brought into a source file from another file, and messages can be printed during the processing of a source file.  The available directives are given on the following pages.

Use	Directives allow you to use more complex structures.

Some of the directives use arguments to determine conditions.  The arguments can be actual arguments, or dummy arguments preceded by question marks (?).

See Also

@Alternate

@Carry

@Const

@Dcset

@Dcstate

@Exit

@Expr

@If

@Ifb

@Ifdef

@Ifiden

@Ifnb

@Ifndef

@Ifniden

@Include

@Irp

@Irpc

@Message

@Onset

@Page

@Radix

@Repeat

@Setsize

@Standard


@Alternate - Alternate Operator Set

Syntax	@ALTERNATE

Use	@ALTERNATE brings an alternate set of operators into effect that replace the normal ABEL-HDL operators if you feel more comfortable with the alternate set because of their familiarity with operators used in other languages.

The alternate operators remain in effect until the @STANDARD directive is issued or the end of the module is reached.

Note:  The use of the alternate operator set precludes use of the ABEL-HDL addition, multiplication and division operators because they represent the OR, AND and NOT logical operators in the alternate set.  The !, &, #, $ and !$ will still work when @alternate is in effect.

The table below summarizes the alternate operator set.

Standard	Alternate

Operator	Operator

!	/	NOT

&	*	AND

#	+	OR

$	:+:	XOR

!$	:*:	XNOR

See Also

@Standard


@Carry - Maximum Bit-width for Arithmetic Functions

Syntax	@Carry expression ; expression	A numeric expression

Use	The @CARRY directive allows you to specify how adders, counters and comparators are generated to reduce the amount of logic required for processing large arithmetic functions.  The number generated by the expression indicates the maximum bit-width to use when performing arithmetic functions.

For example, for an 8-bit adder, a @CARRY statement with an expression which results in 2 would divide the 8-bit adder into four 2-bit adders, creating intermediate nodes.  This would reduce the amount of logic generated.

The statement:

@CARRY 1;

generates chains of one-bit adders and comparators for all subsequent adder and comparator equations, instead of the full look-ahead carry equations normally generated.

This directive automatically generates additional combinational nodes.  Use different values for the @CARRY statement to specify the types of adders and comparators required for the design.  To specify that full lookahead carry should be generated (the default if no @CARRY has been specified) use the statement:

@CARRY 0;

Examples	@carry 2; "generate adder chain
[s8..s0] = [.x.,a7..a0]+[.x.,b7..b0]

See Also

= (Constant Declarations)

Special Constants


@Const - Constant Declarations

Syntax	@CONST  id = expression ;

id	A valid identifier

expression	A valid expression

Use	@CONST allows new constant declarations to be made in a source file outside the normal (and required) declarations section.

The @CONST directive is intended to be used inside macros to define internal constants.  Constants defined with @CONST override previous constant declarations.  Declaring an identifier as a constant in this manner constitutes an error if the identifier was used earlier in the source file as something other than a constant (that is, a macro, pin, device).

Examples

@CONST count = count + 1;

See Also

= (Constant Declarations)

Special Constants


@Dcset - Don't Care Set

Syntax	@DCSET

Use	ABEL-HDL uses don't-care conditions to help in the optimization of partially-specified logic functions. Partially specified logic functions are those that have less than 2n significant input conditions, where n is the number of input signals.  The @dcset option allows the optimization to use 1 or 0 for don't cares to optimize these functions.

Caution:  The @dcset directive overrides Istype 'dc', 'neg' and 'pos' attributes.

See Also

?= and ?:= Assignment Operators

@onset

Truth_Table


Karnaugh Map of @Dcset Example

Expressed as a Karnaugh map, the on-set, off-set and dc-set would appear as follows (with ones indicating the on-set, zeroes indicating the off-set, and dashes indicating the dc-set):

    \ i1 i0
i3 i2\
      \ 00  01  11  10
        \---------------
     00 | 0 | 0 | 0 | - |
        |---|---|---|---|
     01 | - | - | 1 | - |
        |---|---|---|---|
     11 | 1 | - | 1 | 1 |
        |---|---|---|---|
     10 | 0 | - | - | - |
         --- --- --- ---


@DCState

Syntax	@dcstate

Use	When @dcstate is specified, all unspecified state diagram states and transitions are applied to the design outputs as don't-cares.  This option must be used in combination with @dcset or with the 'dc' attribute.

See Also

@DCSET

Istype 'dc'


@Exit - Exit Directive

Syntax	@EXIT

Use	The @exit directive causes the compiler to halt processing of the source file with error bits set. (Error bits allow the operating system to determine that a processing error has occurred.)


@Expr - Expression Directive

Syntax	@EXPR { block } expression;

block	A valid block of text

expression	A valid expression

Use	@Expr evaluates the given expression, and converts it to a string of digits in the default base numbering system. This string and the block are then inserted into the source file at the point at which the @Expr directive occurs. The expression must produce a valid number.

Examples

@expr {Addr} 10+4 ;

Assuming that the default base is base ten, this example causes the text ABC3 to be inserted into the source file.


@If - If Directive

Syntax	@IF expression {block}

expression	A valid expression

block	A valid block of text

Use	@IF is used to include sections of ABEL source code based on the value resulting from an expression. If the expression is non-zero (logical true), the block of code is included as part of the source. Dummy argument substitution is valid in the expression.

Examples

@IF (A>17) {C = D$F;}


@Ifb - If Blank Directive

Syntax	@IFB (arg) {block}

arg	An actual argument or dummy argument preceded by a "?"

block	A valid block of text

Use	@IFB includes the text contained within the block if the argument is blank (has 0 characters).

Examples

@IFB ()
{ text here will be included with the rest of the source file. }

@IFB ( hello )
{ this text will not be included }

@IFB (?A)
{ this text will be included if no value is substituted for A. }

See Also

@ifnb


@Ifdef - If Defined Directive

Syntax	@IFDEF id {block}

id	An identifier

block	A valid block of text

Use	@IFDEF includes the text contained within the block if the identifier is defined.

Examples

A pin 5 ;

@IFDEF A {BASE = ^hE000;}
"the above assignment is made because A was defined

See Also

@ifndef


@Ifiden - If Identical Directive

Syntax	@IFIDEN (arg1,arg2) {block}

arg1,2	Actual arguments or dummy arguments preceded by "?"

block	A valid block of text

Use	The text in the block is included in the source file if arg1 and arg2 are identical.

Examples

@ifiden (?A,abcd) { ?A device 'P16R4'; }

A device declaration for a P16R4 is made if the actual argument substituted for A is identical to abcd.

See Also

@ifniden


@Ifnb - If Not Blank Directive

Syntax	@IFNB (arg) {block}

arg 	An actual argument, or dummy arguments preceded by "?"

block	A valid block of text

Use	@IFNB includes the text contained within the block if the argument is not blank, meaning that it has more than 0 characters.

Examples

@IFNB ()
{ ABEL source here will not be included with the rest of the source file. }

@IFNB ( hello )
{ this text will be included }

@IFNB (?A)
{ this text will be included if a value is substituted for A}

See Also

@ifniden


@Ifndef - If Not Defined Directive

Syntax	@IFNDEF id {block}

id 	An identifier

block	A valid block of text

Use	@IFNDEF includes the text contained within the block if the identifier is undefined. Thus, if no declaration (pin, node, device, macro or constant) has been made for the identifier, the text in the block will be inserted into the source file.

Examples

@IFNDEF A {BASE = ^hE000;"
"if A is not defined, the block is inserted in the text

See Also

@ifb


@Ifniden - If Not Identical Directive

Syntax	@IFNIDEN (arg1,arg2) {block}

arg1,2	Actual arguments, or dummy arguments preceded by "?"

block	A valid block of text

Use	The text in the block is included in the source file if arg1 and arg2 are not identical.

Examples

@ifniden (?A,abcd) { ?A device 'P16R8'; }

A device declaration for a P16R8 is made if the actual argument substituted for A is not identical to abcd.

See Also

@ifiden


@Include - Include Directive

Syntax	@INCLUDE filespec

filespec	A string specifying the name of a file, where the specification follows the rules of the operating system being used

Use	@INCLUDE causes the contents of the file identified by the file specification to be placed in the ABEL source file. The inclusion will begin at the location of the @INCLUDE directive. The file specification can include an explicit drive or path specification that indicates where the file is to be found. If no drive or path specification is given, the file is expected to be on either the default drive or path.

Examples

@INCLUDE 'macros.abl'   "file specification

@INCLUDE '\\incs\\macros.inc' "DOS paths require 2 slashes


@Irp - Indefinite Repeat Directive

Syntax	@IRP dummy_arg ( arg [,arg]...  )  {block}

dummy_arg	A dummy argument

arg	An actual argument, or dummy argument preceded by a "?"

block	A block of text

Use	@IRP causes the block to be repeated in the source file n times, where n equals the number of arguments contained in the parentheses. Each time the block is repeated, the dummy argument takes on the value of the next successive argument.

Examples

@IRP A (1, ^h0A,0) {B = ?A;}

results in:

B = 1 ;
B = ^H0A ;
B = 0 ;

which is inserted into the source file at the location of the @IRP directive. Multiple assignments to the same identifier cause an implicit OR to occur.

See Also

@irpc


@Irpc - Indefinite Repeat, Character Directive

Syntax	@IRPC dummy_arg (arg) {block}

dummy_arg	A dummy argument

arg	An actual argument,  or a dummy argument name preceded by a "?"

block	A valid block of text

Use	@IRPC causes the block to be repeated in the source file n times, where n equals the number of characters contained in arg. Each time the block is repeated, the dummy argument takes on the value of the next successive character.

Examples

@IRPC A (Cat)
{B = ?A ;
       }

results in:

C ;
B = a ;
B = t ;

which is inserted into the source file at the location of the @IRPC directive.

See Also

@irp


@Message - Message Directive

Syntax	@MESSAGE 'string'

string	Any valid string

Use	@Message prints a message specified in string to your monitor. This can be used to monitor the progress of compiling, or to debug complex sequences of directives.

Examples

@message 'Includes completed'


@Onset
@Onset - Disable @DCSET

Syntax	@ONSET

Use	@ONSET disables the effects of @DCSET for subsequent truth tables and state diagrams.  You may enable don't-care optimization with another @DCSET directive.

See Also

@dcset


@Page - Page Directive

Syntax	@PAGE

Use	Send a form feed to the compiler listing file.  If no listing is being created, @page has no effect.


@Radix - Default Base Numbering Directive

Syntax	@RADIX expr ;

expr 	A valid expression that produces the number 2, 8, 10 or 16 to indicate a new default base numbering

Use	@Radix is used to change the default base numbering system. The default is base 10 (decimal). This directive is useful when many numbers need to be specified in a base other than 10. The @radix directive can be issued and all numbers that do not have their base explicitly stated are assumed to be in the new base. (See the chapter "Language Elements.")

Examples

@radix 2 ;        "change default base to binary

@radix 10 ;       "change to decimal


@Repeat - Repeat Directive

Syntax	@REPEAT expr {block}

expr	A valid expression that produces a number

block	A valid block of text

Use	@REPEAT causes the block to be repeated n times, where n is specified by the constant expression.

Examples

@repeat 5 {H,}

results in the text "H,H,H,H,H," being inserted into the source file.


@Setsize - Set Indexing

Syntax	@SETSIZE

Use	The @Setsize directive generates a number corresponding to the number of elements in the expression, which must be a set.  This directive is useful for set indexing operations.

Example

@setsize [a,b,c]

generates the number 3.

For set indexing, the @Setsize directive can be used in macros as follows:

high macro (s) {?s[@setsize(?s); -1..@setsize(?s);/2-1};

The high macro returns the upper half of a set of any size (the high 4 bits of an 8-bit set, for example).

Note: The terminating semicolons are required.

See Also

Set Indexing


@Standard - Standard Operators Directive

Syntax	@STANDARD

Use	@Standard switches the operators in effect back to the ABEL standard operators from the alternate set. The alternate set is chosen with the @Alternate directive.


ABEL-HDL Dot Extensions

Dot extensions provide a means to refer specifically to internal signals and nodes associated with a primary signal in your design.  They more precisely describe the behavior of signals in a logic description and are used to remove ambiguities in equations.

There are two types of dot extensions: pin-to-pin and detailed.  See Pin-to-pin Vs. Detailed Dot Extensions for more information.

Pin-to-Pin Dot Extensions

Dot Ext.	Function

.ACLR 	Asynchronous Reset

.ASET 	Asynchronous Preset

.CLR 	Synchronous Reset

.COM 	Combinational Feedback from flip-flop data input, normalized to the pin value

.FB 	Register Feedback

.SET 	Synchronous Preset

Detailed Dot Extensions

Dot Ext.	Function

.AP 	Asynchronous Preset

.AR 	Asynchronous Reset

.CE 	Clock Enable

.CLK 	Clock Input

.D 	D Flip-flop

.FC 	Flip-flop Mode Control

.J 	J Input to JK Flip-flop

.K 	K Input to JK Flip-flop

.LD 	Register Load Input

.LE 	Latch Enable

.LH 	High Latch Enable

.OE 	Output Enable

.PIN 	Pin Feedback

.PR 	Preset

.Q 	Register Feedback

.R 	R Input to SR Flip-flop

.RE 	Reset

.S 	S Input to SR Flip-flop

.SP 	Synchronous Preset

.SR 	Synchronous Reset

.T 	T (toggle) Input to T Flip-flop

See Also

Pin-to-pin and Detailed Dot Extensions

Dot Extensions for Register Types

Dot Extension Drawings


Dot Extension Schematics

The figures below show the effect of each dot extension.

See Also

Pin-to-pin and Detailed Dot Extensions

Dot Extensions for Register Types

ABEL-HDL Dot Extensions


Device-specific Vs. Architecture-independent Dot Extensions

ABEL-HDL contains a comprehensive set of signal extensions (dot extensions) that can be used to more precisely specify the meaning of a design description. These dot extensions allow you to refer to various circuit elements (such as register clocks, presets, feedback and output enables) that are related to a primary signal.

The dot extensions in ABEL-HDL are divided into two categories: pin-to-pin and detailed:

Pin-to-pin 	Pin-to-pin dot extensions define the function of input and output signals, without considering how the signals are implemented.  Logic descriptions defined pin-to-pin are architecture-independent, and can be easily retargetted to different devices.

Detailed	Detailed dot extensions define the implementation of signals, and require specific device configurations.  You need to know what features are available in the target device, and retargetting your design without modification is usually possible only to devices with similar features.  These dot extensions are also called "device-specific" dot extensions.

You should not mix pin-to-pin and detailed descriptions, since it may result in ambiguous circuits.

In most cases it is possible to describe a circuit using either detailed or pin-to-pin dot extensions. Which form you use depends on the application, and whether you want the application to be capable of being implemented in a wide variety of device architectures.

See Also

Dot Extensions for Register Types

Dot Extension Drawings

ABEL-HDL Dot Extensions


Dot Extensions for Register Types

Pin-to-Pin Combinational Logic

Required	Optional

none	.OE

.PIN

Pin-to-Pin Registered Logic

Required	Optional

.CLK 	.FB

.COM

.PIN

.ACLR/.ASET

.CLR/.SET

Detailed Combinational Logic

Required	Optional

none	.OE

.PIN

Detailed D Flip-flops

Required	Optional

.CLK 	.FC

.D 	.OE

.Q

.SP/.SR

.AP/.AR

.PIN

Detailed JK Flip-flops

Required	Optional

.CLK 	.FC

.J/.K 	.OE

.Q

.SP/.SR

.AP/.AR

.PIN

Detailed SR Flip-flops

Required	Optional

.CLK 	.OE

.S/.R 	.Q

 	.SP/.SR

.AP/.AR

.PIN

Detailed T Flip-flops

Required	Optional

.CLK 	.OE

 .T 	.Q

.SP/.SR

.AP/.AR

.PIN

Gated Clock D Flip-flop

Required	Optional

.CLK 	.CE

.D 	.OE

.Q

 	.PIN


.ACLR and .ASET - Asynchronous Preset and Reset
.ACLR and .ASET - Pin-to-Pin Async. Preset and Reset

Syntax	signal-name.ACLR
signal-name.ASET

Use	Pin-to-pin dot extensions specifying the signal is an asynchronous preset (.ACLR) or asynchronous reset (.ASET).

See Also

Synchronous Preset and Reset

Pin-to-pin Vs. Detailed Dot Extensions


.AP and .AR - Asynchronous Preset and Reset
.AP and .AR - Detailed Asynchronous Preset and Reset

Syntax	signal-name.AP
signal-name.AR

Use	Device-specific dot extensions specifying the signal is an asynchronous preset (.AP) or asynchronous reset (.AR).

See Also

.SP and .SR

.ACLR and .ASET

Pin-to-pin Vs. Detailed Dot Extensions


.CE - Clock Enable

Syntax	signal-name.CE

Use	Device-specific dot extension specifying the signal is a clock enable.

See Also

Pin-to-pin Vs. Detailed Dot Extensions

Dot Extensions for Register Types

.CLK


.CLK - Clock Input

Syntax	signal-name.CLK

Use	Device-specific dot extension specifying the signal is a clock input.

See Also

Pin-to-pin Vs. Detailed Dot Extensions

Dot Extensions for Register Types


.CLR and .SET - Pin-to-Pin Synchronous Preset and Reset

Syntax	signal-name.CLR
signal-name.SET

Use	Pin-to-pin dot extensions specifying the signal is a synchronous preset (.CLR) or synchronous reset (.SET).

See Also

.ACLR and .ASET

.SP and .SR

Pin-to-pin Vs. Detailed Dot Extensions


.COM
.COM - Normalized Combinational Feedback

Syntax	signal-name.COM

Use	Pin-to-pin dot extension for combinational feedback from the flip-flop data input, normalized to the pin value.  Can be used to distinguish between pin (.PIN) and internal logic array (.COM) feedback in pin-to-pin design descriptions.

See Also

.FB and .Q

.PIN


.D - Data Input

Syntax	signal-name.D

Use	Device-specific dot extension for the data input to a D-type flip-flop.

Example

These equations precisrely describe the desired circuit as being a toggling D-type flip-flop that is clocked by the input Clock, assuming Istype 'reg_D,buffer':

Q1.clk = Clock;

Q1.D = !Q1.Q # Preset;

See Also

Pin-to-pin Vs. Detailed Dot Extensions

Dot Extensions for Register Types

.CLK


.FB and .Q - Register feedback

Syntax	signal-name.FB
signal-name.Q

Use	Dot extensions specifying the signal is register feedback.  .FB is pin-to-pin, and signals with this extension are normalized to pin polarity.  .Q is device-specific feedback from the register.

See Also

.COM

Feedback - .Q and .FB

Feedback Normalization

Feedback Without Dot Extensions

Pin-to-pin Vs. Detailed Dot Extensions


.FC - Flip-flop Mode Control

Syntax	signal-name.FC

Use	Device-specific dot extension for a signal used as a flip-flop mode control.

See Also

Pin-to-pin Vs. Detailed Dot Extensions


.J  and .K - Inputs to a JK Flip-flop

Syntax	signal-name.J
signal-name.K

Use	Device-specific dot extensions for signals used as the J (.J) and K (.K) inputs to a JK flip-flop.

See Also

Pin-to-pin Vs. Detailed Dot Extensions

Dot Extensions for Register Types


.LD - Register load input

Syntax	signal-name.LD

Use	Device-specific dot extension indicating a register load input.

See Also

Pin-to-pin Vs. Detailed Dot Extensions


.LE and .LH - Latch-enable Inputs

Syntax	signal-name.LE
signal-name.LH

Use	Device-specific dot extensions for low (.LE) and high (.LH) inputs to a latch.

See Also

Pin-to-pin Vs. Detailed Dot Extensions

Dot Extensions for Register Types


.OE - Output enable

Syntax	signal-name.OE

Use	Pin-to-pin dot extension for an output enable.

Example - Three-state Output Enables

Output enables are described in ABEL-HDL with the .OE dot extension applied to an output signal name. For example,

Q1.OE = !enab;

The equation specifies that the input signal enab is to be used to control the output enable for an output signal named Q1.

Note:  Explicitly stating the value of a fixed output enable restricts the device fitters' ability to map the indicated signal to a simple input pin instead of a three-state I/O pin.

See Also

Pin-to-pin Vs. Detailed Dot Extensions


.PIN - Pin Feedback

Syntax	signal-name.PIN

Use	Pin-to-pin dot extension for pin feedback.

See Also

.COM

Pin-to-pin Vs. Detailed Dot Extensions


.PR - Register Preset
.PR - Register preset (synchronous or asynchronous)

Syntax	signal-name.PR

Use	Device-specific dot extension for an asynchronous or synchronous register preset.

Example

Q2.PR = S & !T

See Also

.ASET

.SET

Pin-to-pin Vs. Detailed Dot Extensions


.S and .R - Inputs to an SR Flip-flop

Syntax	signal-name.S
signal-name.R

Use	Device-specific dot extensions for the S (.S) and R (.R) inputs to an SR flip-flop.

See Also

Pin-to-pin Vs. Detailed Dot Extensions

Dot Extensions for Register Types


.RE - Register reset

Syntax	signal-name.RE

Use	Device-specific dot extension for a synchronous or asynchronous register reset.

Example

Q2.RE = R & !T;

See Also

.ACLR

.CLR

Pin-to-pin Vs. Detailed Dot Extensions


.SP and .SR - Synchronous Preset and Reset

Syntax	signal-name.SP
signal-name.SR

Use	Device-specific dot extensions for the S (.S) and R (.R) inputs to an SR flip-flop.

See Also

.CLR and .SET

Pin-to-pin Vs. Detailed Dot Extensions


.T - T input to a T Flip-flop

Syntax	signal-name.T

Use	Device-specific dot extension for the T input to a T-type (toggle) flip-flop.

See Also

Pin-to-pin Vs. Detailed Dot Extensions

Dot Extensions for Register Types


Designing With FPGAs

ABEL-HDL allows you to generate source files with efficient logic for FPGAs. This section is divided into the following subtopics:

ABEL-HDL for FPGAs

FPGA Design Strategies

Working with Signals

The figure below shows the FPGA design process.


ABEL-HDL for FPGAs

With ABEL-HDL, you can describe your logic functions independent of the architecture in which they will be implemented.  You can then implement your description into a number of different devices (for example, a LCA and an ACT1 device) with no changes in many cases.

ABEL-HDL contains language elements that allow you to take advantage of features specific to particular FPGAs.  For example, if a device directly supports clock enables, you can specify clock enables in your ABEL-HDL source file equations.


FPGA Design Strategies

The following design strategies are helpful when designing for FPGAs.  More detailed information is provided in later sections.

•	Define external and internal signals with pin and node statements, respectively.

•	For state machines and truth tables, include @DCSET or 'dc' attributes if possible, since it usually reduces logic.  @DCSTATE can also be used to reduce the logic for state machine outputs.

•	Use only dot extensions appropriate for FPGA designs.  Information on using dot extensions is provided in the specific FPGA fitter user manuals.

•	Use intermediate signals to create multi-level logic to match FPGA architectures.


Working with Signals

Declaring Signals

Using Intermediate Signals

Example of Intermediate Signals


Declaring Signals

The first step in creating a logic module for an FPGA is to declare the signals in your design.  In ABEL-HDL, you do this with pin and node statements.

Pin Statements 	Indicate external signals (that is, signals used as inputs and outputs to the functional block).  Pin numbers are optional in ABEL-HDL, and are not recommended for FPGAs, since pin statements don't actually generate pins on the device package.  If you declare an external signal as a node instead of a pin, the device fitter may later interpret the signal incorrectly and delete it.

Node Statements Indicate internal signals (that is, signals not accessible by circuitry outside the functional block).  Signals declared as nodes are expected to have a source and loads.

For example, the figure below shows a state machine as a functional block.  State bits S1 through S7 are completely internal; all other signals are external.

Below are the corresponding signal declarations.  The CLOCK, RESET, input, and output signals must connect with circuitry outside the functional block, so they are declared as pins.  The state bits are not used outside the functional block, so they are declared as nodes.

CLOCK, RESET              Pin;
I0,I1,I2,I3               Pin;
O1,O2                     Pin;
S7,S6,S5,S4,S3,S2,S1      Node;


Using Intermediate Signals

An intermediate signal is a combinational signal that is declared as a node and used as a component of other more complex signals in a design.  Intermediate signals minimize logic by forcing it to be factored.  Creating intermediate signals in an ABEL-HDL logic description has the following benefits:

~	Reduces the amount of optimization a device fitter has to perform

~	Increases the chances of a fit

~	Simplifies the ABEL-HDL source file

For large designs, using intermediate signals can be essential.  An expression such as

IF (input==code_1)<|>.<|>.<|>.

generates a product term (AND gate).  If the input is 8 bits wide, so is the AND gate.  If the expression above is used 10 times, the amount of logic generated will cause long run times during compilation and fitting, or may cause fitting to fail. If you write the expression as an intermediate equation,

code_1_found   node;
equations
code_1_found = (input==code_1);

you can use the intermediate signal many times without creating an excessive amount of circuitry.

IF code_1_found . . .

An alternative method of creating intermediate equations is to use the @CARRY  directive.  This directive causes comparators and adders

to be generated using intermediate equations for carry logic, resulting in an efficient multilevel implementation.

In general, you should design for multi-level FPGAs in a multi-level fashion, using intermediate signals as much as possible.  An FPGA device kit fitter is capable of transforming two-level designs into multi-level designs, but it takes a lot of time and sometimes fails.  Rewriting your designs to reflect the multi-level nature of the FPGA architecture often reduces the time for fitting, increases the chance of a fit, and simplifies your design descriptions.

See Also

Example of Intermediate Signals


Example of Intermediate Signals

The schematic below is combinational logic.  Signals A, B, C, D, and E are inputs; X and Y are outputs.  There are no intermediate signals; every declared signal is an input or output to the subcircuit.

Below is the ABEL-HDL declarations and equations that would generate the logic shown in the schematic.

declarations
  A, B, C, D, E  pin;
  X, Y           pin;

equations
  X = (A&B&C) # (B$C);
  Y = (A&D) # (A&E) # (A&B&C);

The next schematic shows the same logic using an intermediate signal, M, which is declared as a node and named, but is used only inside the subcircuit as a component of other, more complex signals.

Below are the declarations and equations that would generate the logic shown in the second schematic.

declarations
  A, B, C, D, E  pin;
  X, Y           pin;
  M              node;

equations
"intermediate signal equations
  M = A&B&C;
  X = M # (B$C);
  Y = (A&D) # (A&E) # M;

Both design descriptions are functionally the same.  Without the intermediate signal, ABEL generates the AND gate associated with (A&B&C) twice, and the device fitter must filter out the common term.  With the intermediate signal, this sub-signal is generated only once as the intermediate signal, M, and the fitter has less to do.

Using intermediate signals in a large design targeted for a complex PLD or FPGA can save fitter optimization effort and time.  It also makes the design description easier to interpret.  As another example, compare the state machine descriptions in No Intermediate Signals  and With Intermediate Signals below.  The description with intermediate signals is easier to read.

No Intermediate Signals

CASE
which_code_enter==from_disarmed_ready:

  CASE
  (sens_code==sens_off) & (key_code!=key_pound)
                        & (key_code!=key_star)
                        & (key_code!=key_none): code_entry_?X  WITH {
                 which_code_enter := which_code_enter; }
  (key_code==sens_off) & (key_code==key_none): code_entry_?Y  WITH {
                 which_code_enter := which_code_enter; }

  (key_code==key_pound) # (key_code==key_star): error;
  (sens_code!=sens_off):  error;
  ENDCASE

which_code_enter==from_armed:

  CASE
  (key_code!=key_pound)
  & (key_code!=key_star)
  & (key_code!=key_none): code_entry_?X  WITH {
                 which_code_enter := which_code_enter; }
  ((key_code==key_pound) # (key_code==key_star)): armed WITH {
                 which_code_enter := which_code_enter; }
  (key_code==key_none): code_entry_?Y  WITH {
                 which_code_enter := which_code_enter; }
  ENDCASE

ENDCASE

With Intermediate Signals

CASE
enter_from_disarmed_ready:
  CASE
  sensors_off & key_numeric: code_entry_?X  WITH {
                  which_code_enter := which_code_enter; }
  sensors_off & key_none: code_entry_?Y  WITH {
                  which_code_enter := which_code_enter; }
  key_pound_star:     error;
  !sensors_off:       error;
  ENDCASE

enter_from_armed:

  CASE
  key_numeric:   code_entry_?X  WITH {
                 which_code_enter := which_code_enter; }

  key_pound_star:armed  WITH {
                 which_code_enter := which_code_enter; }

  key_none: code_entry_?Y  WITH {
                 which_code_enter := which_code_enter; }
  ENDCASE

ENDCASE

Note:  The declarations and equations required to create the intermediate signals used in the above case statements with intermediate signals are given below.

"pin and node declarations
   sens_code_0, sens_code_1,
   sens_code_2, sens_code_3      pin;
   key_code_0, key_code_1,
   key_code_2, key_code_3        pin;

   which_code_enter_0,
   which_code_enter_1,
   which_code_enter_2            node istype 'reg';

"set declarations
   which_code_enter = [which_code_enter_0..which_code_enter_2];
   sens_code = [sens_code_0..sens_code_3];
   key_code  = [key_code_0 ..key_code_3];

"code-entry sub-states
   from_disarmed_ready     = [1, 0, 0];
   from_armed              = [0, 0, 0];
   sens_off                = [0, 0, 0, 0];

"key encoding
   key_pnd   = [1, 1, 0, 0];
   key_str   = [1, 0, 1, 1];
   key_non   = [0, 0, 0, 0];

"intermediate signals
   enter_from_disarmed_ready     node;
   enter_from_armed              node;
   sensors_off                   node;
   key_numeric                   node;
   key_none                      node;
   key_pound_star                node;

equations

"intermediate equations
   enter_from_disarmed_ready = which_code_enter==from_disarmed_ready);
   enter_from_armed = (which_code_enter==from_armed);
   sensors_off    = (sens_code==sens_off);

   key_numeric    = (key_code!=key_pnd)
                  & (key_code!=key_str)
                  & (key_code!=key_non);

   key_none       = (key_code==key_non);

   key_pound_star = (key_code==key_pnd)
                  # (key_code==key_str);


ABEL-HDL Source Structure

This section provides the basic syntax and structure of an ABEL-HDL design description.  For information on specific elements, refer to the Language Reference.  You can create your ABEL-HDL source using any word processor or text editor that produces ASCII files.

Introduction to ABEL-HDL

Basic Syntax

Arguments and Argument Substitution

Comments

Constants

Dot Extensions

Equation Blocks

Expressions

Operators

Sample Module

Sets

Set Indexing


Arguments and Argument Substitution

Variable values can be used in macros, modules and directives.  These values are called the arguments of the construct that uses them.  In ABEL-HDL, there are two types of arguments: actual and dummy. Their definitions are given here.

Dummy argument	An identifier used to indicate where an actual argument is to be substituted in the macro, module, or directive.

Actual argument	The argument (value) used in the macro, directive or module.  The actual argument is substituted for the dummy argument.  An actual argument can be any text, including identifiers, numbers, strings, operators, sets, or any other element of ABEL-HDL.

Dummy arguments are specified in macro declarations and in the bodies of macros, modules and directives.  The dummy argument is preceded by a question mark in the places where an actual argument is to be substituted.  The question mark distinguishes the dummy arguments from other ABEL-HDL identifiers occurring in the source file.

Take for example, the following macro declaration arguments:

OR_EM MACRO (a,b,c) { ?a # ?b # ?c };

This defines a macro named OR_EM that is the logical OR of three arguments. These arguments are represented in the definition of the macro by the dummy arguments, a, b, and c.  In the body of the macro, which is surrounded by braces, the dummy arguments are preceded by question marks to indicate that an actual argument will be substituted.

The equation

D = OR_EM (x,y,z&1);

invokes the OR_EM macro with the actual arguments, x, y, and z&1.  This results in the equation:

D = x # y # z&1;

Arguments are substituted into the source file before checking syntax and logic, so if an actual argument contains unsupported syntax or logic, the compiler detects and reports the error.

Argument Guidelines

•	Dummy arguments are place holders for actual arguments.

•	A question mark preceding the dummy argument indicates that an actual argument is to be substituted.

•	Actual arguments replace dummy arguments before the source file is checked for correctness.

•	Spaces in actual arguments are retained.  Usually spaces will not change the functionality, but they are significant with directives that compare two values, such as @ifiden.

See Also

Module

Macro

Directives


Comments

Comments can be entered two ways:

"	Begin the comment with a double quotation mark and end with the end of the line or another double quotation mark.

//	Begin with a double forward slash and end with the end of the line (this is useful for commenting out lines of ABEL-HDL source files that contain quote-delineated comments).


Sets

A set is a collection of signals and constants.  Any operation applied to a set is applied to each element in the set. Sets simplify ABEL-HDL logic descriptions and test vectors by allowing groups of signals to be referenced with one name.

For example, you could collect the outputs (for example, B0-B7) of an eight-bit multiplexer into a set named MULTOUT, and the three selection lines into a set named SELECT.  You could then define the multiplexer in terms of MULTOUT and SELECT rather than individual input and output bits.

A set is represented by a list of constants and signals separated by commas or the range operator (..) and surrounded by brackets.  For example,

Sample Set	Description

[B0,B1,B2,B3,B4,B5,B6,B7]	outputs (MULTOUT)

[S0,S1,S2]	select lines (SELECT)

The above sets could also be expressed by using the range operator; for example,

[B0..B7]
[S0..S2]

Identifiers used to delimit a range must have compatible names:  they must begin with the same alphabetical prefix and have a numerical suffix.  Range identifiers can also delimit a decrementing range or a range which appears as one element of a larger set; for example,

[A7..A0]             "decrementing range
[Q1,Q2,.X.,A10..A7]  "range within a larger set

For set specifications, the brackets do not denote optional items.  The brackets are required to delimit the set.  ABEL-HDL source file sets are not mathematical sets.

See Also

Set Indexing

Set Operations

Set Assignment and Comparison

Sequence of Evaluation

Limitations on Sets


Set Indexing

Set indexing allows you to access elements within a set.  The following example uses set indexing to assign four elements of a 16-bit set to a smaller set.

declarations
    Set1 = [f15..f0];
    Set2 = [q3..q0];
equations
    Set2 := Set1[7..4];

The numeric values used for defining a set index refer the the bit positions of the set, with 0 being the least significant (left-most) element in the set.

If you are indexing into a set to access a single element, then you can use the following syntax:

declarations
    out1 pin istype 'com';
    Set1 = [f15..f0];
equations
    out1 = Set1[4] == 1;

In this example, a comparator operator (==) was used to convert the single-element set (Set1[4]) into a bit value (equivalent to f4).

See multiply.abl for more examples of set indexing.


Set Operations

Most operators can be applied to sets, with the operation performed on each element of the set, sometimes individually and sometimes according to the rules of Boolean algebra. "Set Operations," found later in this chapter, describes how these operators are applied to sets.

Two-set Operations

For operations involving two or more sets, the sets must have the same number of elements.  The expression, "[a,b]+[c,d,e]," is not supported because the sets have different numbers of elements.

For example, the Boolean equation

Chip_Sel = A15 & !A14 & A13;

represents an address decoder where A15, A14 and A13 are the three high-order bits of a 16-bit address.  The decoder can easily be implemented with set operations.  First, a constant set that holds the address lines is defined so that the set can be referenced by name. This definition is done in the constant declaration section of a module.

The declaration is

Addr = [A15,A14,A13];

which declares the constant set Addr. The equation

Chip_Sel = Addr == [1,0,1];

is functionally equivalent to

Chip_Sel = A15 & !A14 & A13;

If Addr is equal to [1,0,1], meaning that A15 = 1, A14 = 0 and A13 = 1, then Chip_Sel is set to true.  The set equation could also have been written as

Chip_Sel = Addr == 5;

because 101 binary equals 5 decimal.

In the example above, a special set with the high-order bits of the 16-bit address was declared and used in the set operation.  The full address could have been used and the same function arrived at in other ways, as shown below.

Example 1

" declare some constants in declaration section
Addr = [a15..a0];
X = .X.;   "simplify notation for don't care constant
Chip_Sel = Addr == [1,0,1,X,X,X,X,X,X,X,X,X,X,X,X];

Example 2

" declare some constants in declaration section
Addr = [a15..a0];
X =.X.;
Chip_Sel = (Addr >>= ^HA000) & (Addr <<= ^HBFFF);

Both solutions presented in these final two examples are functionally equivalent to the original Boolean equation and to the first solution in which only the high order bits are specified as elements of the set (Addr = [a15, a14, a13]).


Set Assignment and Comparison

Values and sets of values can be assigned and compared to a set.  are given in the table below.  For example,

sigset = [1,1,0] & [0,1,1];

results in sigset being assigned the value, [0,1,0].  The set assignment

[a,b] = c & d;

is the same as the two assignments

a = c & d;
b = c & d;

Numbers in any representation can be assigned or compared to a set.  The preceding set equation could have been written as

sigset = 6 & 3;

When numbers are used for set assignment or comparison, the number is converted to its binary representation and the following two rules apply:

1	If the number of significant bits in the binary representation of a number is greater than the number of elements in a set, the bits are truncated on the left.

2	If the number of significant bits in the binary representation of a number is less than the number of elements in a set, the number is padded on the left with leading zeroes.

Thus, the following two assignments are equivalent:

[a,b] = ^B101011;	"bits truncated to the left
[a,b] = ^B11;

And so are these two:

[d,c] = ^B01;
[d,c] = ^B1;	"compiler will add leading zero

See Also

Supported Set Operations


Supported Set Operations

Operator	Example	Description

=	A = 5	combinatorial assignment

:=	A := [1,0]	registered assignment

?=	A ?= [1,0]	combinatorial don't care assignment

?:=	A ?:= 5	registered don't care assignment

!	!A	NOT: ones complement

&	A & B	AND

#	A # B	OR

$	A $ B	XOR: exclusive OR

!$	A !$ B	XNOR: exclusive NOR

-	-A	negate

-	A - B	subtraction

+	A + B	addition

==	A == B	equal

!=	A != B	not equal

<	A < B	less than

<=	A <= B	less than or equal

>	A > B	greater than

>=	A >= B	greater than or equal


Sequence of Evaluation

Operators can act differently when used with sets depending on the types of its arguments.  When a set is written

[a, b, c, d]

"a" is the MOST significant bit and "d" is the LEAST significant bit.

The result, when most operators are applied to a set, will be another set. The result of the relational operators (==, !=, >>, >>=, <<, <<=) is a value: TRUE (all ones) or FALSE (all zeros), which is truncated or padded to as many bits as needed.  The width of the result is determined by the context of the relational operator, not by the width of the arguments.  See examples below.

The different contexts of the AND (&) operator and the semantics of each usage are described below.

& Expression	Example	Result

signal & signal	a & b	The expression is TRUE if both signals are TRUE.

signal & number	a & 4	The number is converted to binary and the least significant bit is used.  The expression becomes a & 0, then is reduced to 0 (FALSE).

signal & set      	a & [x, y, z]	The signal is distributed over the elements of the set to become [a & x, a & y, a & z]

set & set         	[a, b] & [x, y]	The sets are ANDed bit-wise resulting in: [a & x, b & y].  An error is displayed if the set widths do not match.

set & number    	[a, b, c] & 5	The number is converted to binary and truncated or padded with zeros as needed to match the width of the set. The sequence of transformations is
[a, b, c] & [1, 0, 1]
[a & 1, b & 0, c & 1]
[a, 0, c]

number & number	9 & 5	The number is converted to binary and the least significant bit is used, so this expression becomes 1 & 1, which is reduced to 1 (TRUE).

Some example equations:

select = [a15..a0] == ^H80FF

select (signal) is TRUE when the 16-bit address bus has the hex value 80FF.  Relational operators always result in a single bit.

[sel1, sel0] = [a3..a0] >> 2

The width of the "sel" set and the "a" set are different, so the "2" is expanded to four bits (of binary) to match the size of the "a" set. Both sel1 and sel2 are true when the value of the four "a" lines (taken as a binary number) are greater than 2.  The result of the comparison is a single-bit result which is distributed to both members of the set on the output side of the equation.

[out3..out0] = [in3..in0] & enab

If enable is TRUE, then the values on "in0" through "in3" are seen on the "out0" through "out3" outputs.  If enable is FALSE, then the outputs are all FALSE.


Limitations/ Restrictions on Sets
Limitations on Sets

If you have a set assigned to a single value, the value is padded with 0s and then applied to the set.  For example,

[A1,A2,A3] = 1

is equivalent to

A1 = 0
A2 = 0
A3 = 1

which may not be the intended result.  If you want 1 assigned to each member of the set, you'd need binary 111 or decimal 7.  Since the widths of expression arguments are determined from context, there are some cases where the results are not as you might expect.  For example, define count as a 3-bit set:

count = [a,b,c]

Then the following expression has a width of one since relational operators evaluate to a single-bit result:

9 & (count == 0)

It is expanded as follows:

9 & ( !a & !b & !c )
1 & !a & !b & !c


Sequence of Evaluation

The results of using an operator depend on the sequence of evaluation.  Without parentheses, operations are performed from left to right. Consider the following two equations.  In the first, the constant 1 is converted to a set; in the second, the 1 is treated as a single bit.

Equation 1:  The first operation is [a, b] & 1, so 1 is converted to a set [0, 1].

[x1, y1] = [a, b] & 1 & d
         = ([a, b] &    1  ) & d
         = ([a, b] & [0, 1]) & d
         = ([a & 0,  b & 1]) & d
         =  [  0  ,    b  ]  & d
         =  [0 & d, b & d]
         =  [0, b & d]

 x1 = 0
 y1 = b & d

Equation 2:  The first operation is 1 & d, so one is treated as a single bit.

[x2,y2] =  1 & d  & [a, b]
        = (1 & d) & [a, b]
        =    d    & [a, b]
        =   [d & a, d & b]

x2 = a & d
y2 = b & d

If you are unsure about the interpretation of an equation, try the following hints:

1	Fully parenthesize your equation. Errors can occur if you are not familiar with the precedence rules in Operator Priorities.

2	Write out numbers as sets of 1s and 0s instead of as decimal numbers.  If the width is not what you expected, you will get an error message.


Sample Source File

Module sample
Title 'Sample Source File'
Declarations
I1..I3, Clk   Pin  11..13, 1 ; " range operator used for I1, I2, I3
S1..S3        Pin  24,25,34  Istype 'reg_d'  ;
C = .C.  ;    "constant .C. mapped to C identifier
Set1 = [S1..S3] ;
Set2 = [I3,I1,I2];
Equations
Set1.clk = Clk ;
Set1 = Set2;
Test Vectors ([Clk,Set1]->[Set2])
              [ C , 3  ]->[  3 ];
End sample


Equation Blocks

Equation blocks let you specify more complex functions and improve the readability of your equations.  An equation block is enclosed in braces ({}), and is supported wherever a single equation is supported.  Within a conditional expression, such as If-Then, Case, or When-Then, equation blocks result in logic functions that are logically ANDed with the conditional expression that is in effect.

Example

state 5 : IF a == 1 then 1
                    WITH {x : = 1 ;
                         y : = 1 ;};
          ELSE 2   WITH {x : = 0 ;
                        y : = 1 ;};

See Also

Case

If-Then-Else

When-Then-Else

With


Constants

Constant, non-changing values can be used in ABEL-HDL logic descriptions.  Constant values are used in assignment statements, truth tables and test vectors, and are sometimes assigned to an identifier that then denotes that value throughout a source file.  Constant values can be numeric, or one of the non-numeric special constant values.

See Also

Special Constants

Constant Declarations


Special Constants

Constant	Description

.C.	Clocked input (low-high-low transition)

.D.	Clock down edge (high-low transition)

.F.	Floating input or output signal

.K.	Clocked input (high-low-high transition)

.P.	Register preload

.SV#	# = 2 through 9.  Drive the input to super voltage 2 through 9.

.U.	Clock up edge (low-high transition)

.X. 	Don't care condition

.Z.	Tristate value

Special constants must be referenced with surrounding periods, and can be upper- or lowercase.

You can assign an identifier to a special constant to simplify entry.  For example, declaring C = .C. allows you to use C without the surrounding periods to indicate the special constant value .C.

See Also

Constants

Constant Declarations


Operators

ABEL-HDL operators are divided into four basic types: logical, arithmetic, relational, and assignment.  The table below shows all of the operators, and each type is discussed in a separate topic.

Logical	Arithmetic	Relational	Assignment	Range

!	-	==	=	..

&	+	!=	:=

#	*	<	?=

$	/	<=	?:=

!$	%	>

<<	>=

>>

See Also

Logical Operators

Arithmetic Operators

Relational Operators

Assignment Operators

Range Operator

Expressions

Operator Priorities

How Equations Use Expressions


Logical Operators

Logical operators are used in expressions.  ABEL-HDL incorporates the standard logical operators listed below.  Logical operations involving operands of more than one bit are performed bit by bit.  For alternate operators, refer to the @Alternate directive.

Operator	Result	Description

!	NOT: 	ones complement	exclamation point

&	AND	ampersand

#	OR	pound sign

$	XOR: 	exclusive OR	dollar sign

!$	XNOR: 	exclusive NOR	exclamation point/dollar sign

See Also

Arithmetic Operators

Relational Operators

Assignment Operators


Arithmetic Operators

Operator	Example	Result	Description
-	-A	Twos complement (negation)	dash (minus sign)
-	A-B	Subtraction	dash
+	A+B	Addition	plus sign

Not Valid for Sets

Operator	Example	Result	Description
*	A*B	Multiplication	asterisk
/	A/B	Unsigned integer division	forward slash
%	A%B	Modulus: remainder from /	percent sign
<<	A<<B	Shift A left by B bits	double left angle bracket
>>	A>>B	Shift A right by B bits	double right angle bracket

Note:  A minus sign has a different significance depending on how you use it. When used with one operand, it indicates that the twos complement of the operand is to be formed.  When the minus sign is found between two operands, the twos complements of the second operand is added to the first.

Arithmetic operators define arithmetic relationships between items in an expression.  The shift operators are included in this class because each left shift of one bit is equivalent to multiplication by 2 and a right shift of one bit is the same as division by 2.

Division is unsigned integer division: the result of division is a positive integer.  The remainder of a division can be obtained by using the modulus operator, "%."  The shift operators perform logical unsigned shifts.  Zeros are shifted in from the left during right shifts and in from the right during left shifts.

See Also

Logical Operators

Relational Operators

Assignment Operators


Relational Operators

Operator	Result	Description
==	Equal	Double equal sign
!=	Not equal	exclamation point/equal sign
<	Less than	left angle bracket
<=	Less than or equal	left angle bracket/equal sign
>	Greater than	right angle bracket
>=	Greater than or equal	right angle bracket/equal sign
Relational operators are used to compare two items in an expression.  Expressions formed with relational operators produce a Boolean true or false value.

All relational operations are unsigned. For example, the expression !0 > 4 is true since the complement of !0 is 1111 (assuming 4 bits of data), which is 15 in unsigned binary, and 15 is greater than 4.  For the purpose of this example, a four-bit representation was assumed; in actual use, !0, the complement of 0, is 32 bits all set to 1.

Examples

Expression	Value

2 == 3	False

2 != 3	True

3 < 5	True

-1 > 2	True

The logical values, true and false, are represented internally by numbers. Logical true is -1 in twos complement: all 32 bits are set to 1.  Logical false is 0 in twos complement so all 32 bits are set to 0.  This means that an expression producing a true or false value (a relational expression) can be used anywhere a number or numeric expression could be used and -1 or 0 will be substituted in the expression depending on the logical result.

For example, A = D $ (B == C); means that

∼	A equals the complement of D if B equals C

ˆ∼	A equals D if B does not equal C.

When using relational operators, always use parentheses to ensure the expression is evaluated in the order you expect.  The logical operators & and # have a higher priority than the relational operators.  The following equation

Select = [A15..A0] == ^hD000 # [A15..A0] ==<N>^h1000;

has the default parentheses grouping

Select = [A15..A0] == (^hD000 # [A15..A0]) ==<N>^h1000;

which is not the intended equation.  To get the desired results, write the equation as follows:

Select = ([A15..A0] == ^hD000) # ([A15..A0] ==<N>^h1000);

See Also

Logical Operators

Arithmetic Operators

Assignment Operators


Assignment Operators

Operator	Description
=	Combinational or detailed assignment for on-set
:=	Implied registered pin-to-pin assignment for on-set
?=	Combinational or detailed assignment for dc-set
?:=	Implied registered pin-to-pin assignment for dc-set

CAUTION:  The := and ?:= operators are used only when writing pin-to-pin registered equations.   If you want to use detailed dot extensions, use the = and ?= operators.

Assignment operators are a special class of operators used in equations rather than in expressions.  Equations assign the value of an expression to output signals.  See "Equations" below for a complete discussion of equations.  There are two assignment operators, combinational and registered.  Combinational or immediate assignment occurs without any delay as soon as the equation is evaluated. Registered assignment occurs at the next clock pulse from the clock associated with the output.

Don't-care Assignment Operators (?= and ?:=)

These assignment operators allow you to fully specify outputs in equations.  For example, in the following truth table, the output F is fully specified:

TRUTH_TABLE ([A,B]->[F]);
             [1,1]-> 0  ; "off-set
             [1,0]-> 1  ; "on-set
             [0,1]-> 1  ; "on-set

The equivalent functionality can be expressed in equations:

@DCSET
F  =  A & !B # !A & B; "on-set
F ?= !A & !B;          "dc-set

Note:  Specifying both the on-set and the don't-care set conditions enhances optimization.

CAUTION:  With equations, @DCSET or ISTYPE 'dc' must be specified or the ?= equations are ignored.

See Also

Logical Operators

Arithmetic Operators

Relational Operators


Range Operator

The range operator indicates a range of numbers.  For example, specifying the set

[A7..A0]

is equivalent to specifying the set

[A7, A6, A5, A4, A3, A2, A1, A0]

The range operator is supported in sets and pin and node declarations.

See Also

Set Indexing


Expressions

Expressions are combinations of identifiers and operators that produce one result when evaluated.  Any logical, arithmetic or relational operators may be used in expressions.

Expressions are evaluated according to the particular operators involved.  Some operators take precedence over others, and their operation is performed first.  Each operator has been assigned a priority that determines the order of evaluation.


Operator Priority

The table below summarizes the logical, arithmetic and relational operators, presented in groups according to their priority.  Priority 1 is the highest priority (performed first), and priority 4 is the lowest (performed last).  With two operators of the same priority, the operations are performed left to right.

Priority	Operator	Description

1	-	negate

1	!	NOT

2	&	AND

2	<<	shift left

2	>>	shift right

2	*	multiply

2	/	unsigned division

2	%	modulus

3	+	add

3	-	subtract

3	#	OR

3	$	XOR: exclusive OR

3	!$	XNOR: exclusive NOR

4	==	equal

4	!=	not equal

4	<	less than

4	<=	less than or equal

4	>	greater than

4	>=	greater than or equal

When you have operators of the same priority in the same expression, the operations are performed from left to right.  You can use parentheses to change the order of evaluation, with the operation in the innermost set of parentheses performed first.  Some examples of  expressions are given below.  Note how the order of operations and the use of parentheses affect the evaluated result.

Expression	Result	Description

2 * 3/2	3	operators with same priority

2 * 3 / 2	3	spaces are insignificant

2 * (3/2)	2	fraction is truncated

2 + 3 * 4	14	multiply first

(2 + 3) * 4	20	add first

2#4$2	4

2#(4$2)	6

2 == ^HA	0	false

14 == ^HE	-1	true

See Also

Logical Operators

Arithmetic Operators

Relational Operators

Assignment Operators


How Equations Use Expressions

Equations assign the value of an expression to a signal or set of signals in a logic description.  The identifier and expression must follow the rules already established for those elements.

Equations use the assignment operators = and ?= (combinational), and := and ?:= (registered).

The complement operator, "!," can be used to express negative logic.  The complement operator precedes the signal name and implies that the expression on the right of the equation is to be complemented before it is assigned to the signal.  Use of the complement operator on the left side of equations is provided as an option; equations for negative logic parts can just as easily be expressed by complementing the expression on the right side of the equation.

See Also

Equations

When-Then-Else

Assignment Operators


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See Also

Changing How Many Files Are Listed


Changing How Many Files Are Listed

You can control how many files are listed in the file listing by editing the [options] section of the initialization file:

mru-list-size 	Change this value to set the maximum number of filenames the Text Editor will record.  You can set this to any value between 0 and 64.

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Selects all of the text in the active file.


Edit: Select Word (Text Editor)
Edit: Select Word

Selects the word to the right of the cursor in the active file.


Edit: Delete Line (Text Editor)
Edit: Delete Line

Deletes the line that the cursor is on.

Shortcuts

Command key:	Shift+Ctrl+K


Edit: Delete to EOL (Text Editor)
Edit: Delete to EOL

Delete all text from the cursor to the end of the line.

Shortcuts

Command key:	Ctrl+K


Edit: Find (Text Editor)
Edit: Find

Finds a text string in the active file, starting at the cursor.  The Find dialog box contains the following elements:

Item	Function

Find What	Enter the text string to find

Match Case	Toggle whether Find matches only the exact case of the text string

Direction	Specify which direction to search.  Up searches backwards from the cursor; down searches forward from the cursor.

Find Next Button	Find the next occurrence of the text string in the active file

Cancel Button	Cancel the Find function

Help Button	Display this help topic

Shortcuts

Command key:	F2

Toolbar:


Edit: Replace (Text Editor)
Edit: Replace

Finds a text string in the active file, starting at the cursor, and replaces it with the specified replacement text string.  The Replace dialog box contains the following elements:

Item	Function

Find What	Enter the text string you want to search for

Replace With	Enter the replacement text

Match Case	Toggle Find between matching the exact case of the text string or ignoring case

Find Next Button	Find the next occurrence of the text string in the active file

Replace Button	Replace the current occurrence

Replace All Button	Replace all occurrences of the find string

Cancel Button	Cancel the Find function

Help Button	Display this help topic

Shortcuts

Command key:	F3

Toolbar:


Edit: Repeat Last Find (Text Editor)
Edit: Repeat Last Find

Finds the next occurrence of the text string last entered with the Find command.

Shortcuts

Command key:	Shift+F2

Toolbar:	Shift+


Edit: Repeat Last Replace (Text Editor)
Edit: Repeat Last Replace

Replaces the next occurrence of the last entered text string with the Replace command.

Shortcuts

Command key:	Shift+F3

Toolbar:	Shift+


Edit: Go To Line (Text Editor)
Edit: Go To Line

Enters the Go To Line dialog box, which displays the line the cursor is currently on (Current Line) and the last line the cursor was on (Last Line).

Type in a line number to go to.  To select all text between the current cursor position and the go to line, check the Extend Selection check box.

Shortcuts

Command key:	F5


Edit: Text

Changes case or indenting of selected text.


View Menu

Status Bar

Toolbar


View: Status Bar

Toggles the display of the status bar.


View: Toolbar

Specifies where the toolbar is displayed. You can also use the hand-cursor to click on the toolbar and drag it to a new display position. To change from a floating display, move the floating window beyond the edge where you want it anchored.


Templates Menu

Attach File

Detach File

Create File

Save File

Insert

Edit

New

Store

Store As

Delete

Insert Mark

Find Mark


Templates: Attach File (Text Editor)
Templates: Attach File

Loads a template file into memory, allowing you to access the templates within the file.


Templates: Detach File (Text Editor)
Templates: Detach File

Unloads a template file.  If you are currently editing templates in the file, before unloading the file you must:

1	Store the edited templates using the Store and Store As commands.

2	Save the template file using the Save command.


Templates: Create File (Text Editor)
Templates: Create File

Creates and loads an empty template file by asking you for the filename. You can then create templates and store them in the new template.


Templates: Save File (Text Editor)
Templates: Save File

Saves any changes to the loaded template file after you have edited the template contents.


Templates: Insert (Text Editor)
Templates: Insert

Inserts a template from a loaded template file into the active window after the cursor.

Shortcuts

Command key:	F9

Toolbar:


Templates: Edit (Text Editor)
Templates: Edit

Edits a template from a loaded template file in a new window.  When you are finished editing, use the Store command to update the loaded template file.  If you want the changes to be permanent, use the Save command (in addition to the Store command) to save the altered template file.

Shortcuts

Toolbar:	Ctrl+


Templates: New (Text Editor)
Templates: New

Opens an empty window where you can enter a new template.  To name the new template and associate it with a template file, select Store As.

Shortcuts

Toolbar:	Shift+


Templates: Store As (Text Editor)
Templates: Store

Updates the loaded template file with a changed template for the current session.  To save changes permanently, select Save and write the loaded template to disk.


Templates: Store As (Text Editor)
Templates: Store As

Stores the active template in a loaded template file with a new name.  To save changes permanently, select Save and write the loaded template to disk.


Templates: Delete (Text Editor)
Templates: Delete

Deletes templates from loaded template files. To save the deletions permanently, select Save and write the loaded template to disk.


Templates: Insert Mark (Text Editor)
Templates: Insert Mark

Inserts a template mark in the active template at the cursor.  Use template marks to mark places where you need to enter variables in your template.  Then, each time you load the template, use Find Mark to jump to and highlight template marks to easily enter variables.

Shortcuts

Command key:	F6


Templates: Find Mark (Text Editor)
Templates: Find Mark

Jumps to and highlights the next template mark.  Start typing to replace the template mark with the variable you want to use.

Shortcuts

Command key:	F4


Tools Menu

Keyboard Recorder

Use the keyboard recorder to record keystrokes while editing a file. You can start and stop the recorder, and replay the recorded keystrokes from the Tools menu.


Options Menu

File and Window Modes

Screen Font

Key Mapping


Options: File and Window Modes (Text Editor)
Options: File and Window Modes

Configures Text Editor operation.  The Viewer Configuration dialog box contains the following items:

Item	Function

Set Modes For 	Specifies what you are setting the configuration for

Display/Input Modes	Configures how files are displayed and edited

Screen Formatting	Configures how files are formatted for the screen

Printing	Sets printing options

File Save Configuration	Configures how files are saved, and whether backup
files are made

Buttons	Indicates what to do with the configuration.


Set Modes For (Text Editor)
Set Modes For

Set Type	Configuration Applies To

File Type	Files with a specified extension that is recognized by the Text Editor  (a period must separate the filename from the extension)

Other Types	Files with extensions not recognized by the Text Editor

New Files	Any new files created in the Text Editor

Current File	The file that is currently active


Display/Input Modes (Text Editor)
Display/Input Modes

Display/Input Mode	Function

Auto indenting	If enabled, the cursor will remain indented after a tabbed line until two consecutive returns are entered

Strip trailing spaces	If enabled, spaces will be stripped from the ends of lines in the file during save operations

Show line numbers	If enabled, line numbers will be displayed on the files

Overwrite	If enabled, the editor is in overwrite mode (typing replaces text ahead of the cursor)

Language	Not used


Screen Formatting (Text Editor)
Screen Formatting

Screen Formatting	Function

Tab Size	Specifies how many spaces are entered when a tab character is pressed.

Soft Tabs	If enabled, tabs are entered as spaces.

Wrapping Enabled	If enabled, entered text is automatically wrapped at the specified column

Column	Specifies the column to wrap text at

See Also

Status Bar


Printing Configuration (Text Editor)
Printing Configuration

Printing Configuration	Function

Page headers	Prints page headers

Wrap long lines	Wraps long lines during printing.  If disabled, limits printed character strings to the width of one displayed page.  Lines that require more than a single page width will be incomplete


File Save Configuration (Text Editor)
File Save Configuration

File Save Configuration	Function

Save in UNIX format	Saves files of the specified type in UNIX file format

Backup when saving	Creates a backup file when saving

Save at intervals	Saves open files at specified intervals (in minutes)


Configuration Buttons (Text Editor)
Configuration Buttons

Button	Function

Apply	Applies the selected configuration to the active file

Delete	Deletes the file type configuration

Save	Saves the configuration for the specified file type

Close	Closes the dialog box and returns to the Text Editor

Help	Displays Viewer Configuration help


Options: Screen Font (Text Editor)
Options: Screen Font

Changes the screen font to the requested font.

ANSI, OEM, and System change the font immediately.  Other brings up a Font Change dialog box:

Item	Function

Font	Selects the type of font

Font Style	Selects the font style

Size	Selects the point size of the font

Sample	Shows what the selected font looks like

OK	Changes the screen font

Cancel	Cancels the font change

Help	Displays this help topic


Keyboard Mapper
Options: Keyboard Mapping

This dialog box allows you to assign editing and program functions to key combinations.  Click on parts of the dialog box, below, for an explanation of  the part's function.

See the Function Reference for explanations of each function and Default Key Mappings for the default mappings.


Available Functions

Lists functions that can be mapped to keys.


Now mapped from

Lists the key mappings for the highlighted function in the Available Functions List.


Available Keys

Lists all of the key combinations available for mapping.


Map Button

Maps the highlighted key combination in the Available Keys list to the highlighted function in the Available Functions List.


Unmap Button

Removes the mapping of the highlighted function to the highlighted key combination in the Mapped To list.


Show on menu

Indicates whether the selected key mapping should be displayed on the menus.  This check box is only available when the highlighted function is a menu item.


Keys in use

Indicates the keys already mapped to functions.

Mapped to

Unmap

Remap

Unmap All


Mapped to

Indicates the function mapped to the key shown in the Keys In Use list.


Unmap Key

Removes the mapping of the Mapped to function from the key combination indicated under Keys in Use.


Remap Key

To remap a key combination:

1	Select a key combination from the Keys In Use list.

2	Select a function from the Available Functions list at the top of the dialog box.

3	Click on the Remap button in the Keys In Use section


Unmap All

Removes all current key mappings.


Reset Button

Resets key mappings to the default configuration.


Load Button

Loads a saved key mapping.


Prefix Keys Button

Sets the prefix for two-character key combinations, extending the available key combinations for mapping.  When you enable a prefix from the Prefix Keys dialog box, the Available Keys listing will be updated with the new key combinations.


Save Button

Saves the key mapping.


Save As Button

Saves the key mapping to a different filename.


Close Button

Closes the Key Mapping dialog box.


Help Button

Displays this help topic.


Window Menu

Manages the windows in the Text Editor.

Command	Function

New Window	Duplicates the active window so you can view two parts of it at once

Tile Horizontal (Shift+F4) 	Arranges open files horizontally on the screen.

Tile Vertical	Arranges open files vertically on the screen

Cascade (Shift+F5)	Arranges open files so their title bars cascade (only the top file text is visible)

Iconize All	Minimizes all open files to icons

Arrange Icons	Straightens out icons

Next	Makes the next window active

Close	Closes the active window

Widen 	Widens the active window to the full width of the Text Editor window

Open Windows listing	Lists all open file windows.  (Select one to make it the active window.)


Help Menu

Command	Displays

Contents (F1) *	Text Editor Menus Help Contents

Search for Help On...	Text Editor Help Search List

How to Use Help	Microsoft's Help On Help

DesignDirect Product	DesignDirect Help

ABEL-HDL Language	Help on ABEL-HDL Language Syntax

Verilog Language Index	This feature is not supported in this release

VHDL Language Index	VHDL Reference Help

About Text Editor	Version Information

* You can select text and press F1 to go directly to syntax help on that text.


Edit Window

You can edit many files in the Text Editor at once, each displayed in their own window.  When editing many files:

•	Remember that most menu items run only on the active file

•	Use the Window menu to manage viewing windows


Status Bar

The status bar displays the current configuration of the Text Editor and indicates the function of menu items and icons when they are selected.  You can change some status fields by double-clicking in the field.  The mouse cursor is an arrow over changeable fields, and a small X over non-changeable fields.  Changeable fields are indicated below by a (C), following the "Displays" description.

Status Field	Displays

Ln # Col #	Line and column of cursor (C)

## 	Number of lines in the file

RO/WR	Read-only or Write (C)

No Wrap/Wrap 72	Do not wrap paragraphs/Wrap paragraphs at column 72 (C)

DOS/UNIX	Save files in DOS or UNIX file format (C)

INS/OVR	Insert or Overwrite editing mode (C)

NUM	Status of Number Lock key


Keyboard Mapper Function Reference
Keyboard Mapping Function Reference

The Project Navigator Text Editor allows you to map keyboard keys or key sequences to the following functions, which appear in the functions list of the key mapping dialog box.

Not all the functions that you can map to keys have equivalent menu commands

CaretDown	Moves the cursor one line down

CaretDownSelect	Moves the cursor one line down, extending the selection

CaretEnd	Moves the cursor to the end of the current line

CaretEndSelect	Moves the cursor to the end of the current line, extending the selection

CaretHome	Moves the cursor to the start of the current line

CaretHomeSelect	Moves the cursor to the start of the current line, extending the selection

CaretLeft	Moves the cursor one character to the left

CaretLeftSelect	Moves the cursor one character to the left, extending the selection

CaretLeftWord	Moves the cursor one word to the left

CaretLeftWordSelect	Moves the cursor one word to the left, extending the selection

CaretPageDown	Moves one page down in the current file

CaretPageUp	Moves one page up in the current file

CaretRight	Moves the cursor one character to the right

CaretRightSelect	Moves the cursor one character to the right, extending the selection

CaretRightWord	Moves the cursor one word to the right

CaretRightWordSelect	Moves the cursor one word to the right, extending the selection

CaretUp	Moves the cursor one line up

CaretUpSelect	Moves the cursor one line up, extending the selection

EditCancelSelection	Removes any highlight from selected text in the current window

EditCMatchBrace	When used with a window that has the C language type associated with it, moves the cursor to a matching brace character

EditCopy	Copies the selected text to the clipboard

EditCut	Copies the selected text to the clipboard and deletes it

EditDeleteSelection	Deletes the selected text

EditDeleteBackwards	Deletes the character to the left of the cursor

EditDeleteForwards	Deletes the character to the right of the cursor

EditDeleteLine	Deletes the whole of the line that the cursor is in

EditDeleteToEndOfLine	Deletes from the position of the cursor to the end of the current line

EditGotoLine	Starts a dialog that prompts for the line number to go to in the current file

EditGotoEnd	Moves to the end of the current file

EditGotoEndSelect	Moves to the end of the current file, extending the selection

EditGotoStart	Moves to the start of the current file

EditGotoStartSelect	Moves to the start of the current file, extending the selection

EditMarkUnchanged	Removes the Text Editor's indication that the current file has been altered

EditNewLine	Inserts a new line character at the position of the cursor

EditPaste	Pastes the contents of the clipboard into the current file at the position of the cursor

EditSearch	Searches for a string in the current file

EditSelectWord	Selects the whole word that the cursor is currently within

EditShowNextLine	Scrolls the window upwards to show the next line in the file. The cursor remains in the same place within the file

EditShowNextPage	Scrolls the window upwards to show the next page in the file. The cursor remains in the same place within the file

EditShowPreviousLine	Scrolls the window downwards to show the previous line in the file. The cursor remains in the same place within the file

EditShowPreviousPage	Scrolls the window downwards to show the previous page in the file. The cursor remains in the same place within the file

EditSplitLine	Splits the current line at the position of the cursor, leaving the cursor unmoved

EditRepeatLastFind	Repeats the last find operation

EditRepeatLastReplace	Repeats the last replace operation

EditReplace	Replaces occurrences of one string with another string

EditTextIndent	Indents the current line, or all the lines in a selection, by one tab stop

EditTextLowercaseSelection	Converts all the letters in the current selection to lower case

EditTextTransposeCharacters	Exchanges the character under the cursor with the one to its left

EditTextUndent	Removes indentation of the current line, or all the lines in a selection, by one tab stop

EditTextUppercaseSelection	Changes all the text that is currently selected to be upper case

ExecConfigureTools	Starts a dialog to configure details of program development tools

ExecControlPanel	Starts the Windows Control Panel

ExecDOSCommand	Runs a DOS command, capturing output in an edit window

ExecDOSPrompt	Runs a DOS command-line shell

ExecLaunchApp	Starts a Windows or DOS application to run independently of the Text Editor

ExecLaunchTool	Starts a program development tool

ExecFileManager	Runs the Windows File Manager

ExecRecordPlay	Replays the last recorded keyboard macro

ExecRecordStart	Starts recording keystrokes and menu selections

ExecRecordStop	Stops recording keystrokes and menu selections

ExecRepeatDOSCommand 	Repeats the last DOS command run with the ExecDOSCommand function

FileAbandon	Closes the file being edited in the current window, discarding any unsaved changes

FileClose	Closes the file being edited in the current window, prompting if there are unsaved changes

FileCloseAll	Closes all the files being edited, prompting if any of them contain unsaved changes

FileExit	Exits the Text Editor

FileInsert	Inserts a file into the current one at the position of the cursor

FileMail	Mails the current file

FileName	Changes the name of the file associated with the current window

FileNew	Creates a new empty edit window for an unnamed file

FileOpen	Opens an existing file for editing

FilePrint	Prints the current file

FilePrintSetup	Runs a dialog that allows printer information to be configured

FileSave	Saves the current file to disk, provided that it has been altered

FileSaveAs	Saves the current file to disk, allowing the output file name to be specified

FileSaveAll	Saves all altered files and templates

FileView	Opens an existing file in read-only mode

FileWrite	Writes a file to disk whether or not it has been changed, allowing you to specify the name of the output file

HelpAbout	Shows the Text Editor About box

HelpContents	Displays the Text Editor Help File at the Contents topic

HelpOnHelp	Starts the Windows help engine to give help about itself

HelpUserDefined1	Starts the Windows help engine, using the first help file configured in the [help-files]ini_help_files section of the initialization file

HelpUserDefined2	Starts the Windows help engine, using the second help file configured in the [help-files]ini_help_files section of the initialization file

HelpUserDefined3	Starts the Windows help engine, using the third help file configured in the [help-files]ini_help_files section of the initialization file

HelpUserDefined4	Starts the Windows help engine, using the fourth help file configured in the [help-files]ini_help_files section of the initialization file

HelpUserDefined5	Starts the Windows help engine, using the fifth help file configured in the [help-files]ini_help_files section of the initialization file

OptionsCurrent	Starts a dialog to change the current window and file modes

OptionsDefault	Starts a dialog to change the window modes for specific file types

OptionsKeyMappings	Starts a dialog to change the mapping of keys to functions

OptionsPrefixKeys	Starts a dialog that allows the user to define what prefix keys are active

OptionsResetModes	Sets the window modes for the current window, and the file modes for the file that it is showing, to those appropriate for the file's type

OptionsScreenFontAnsi	Sets the screen font to be the standard non-proportional ANSI font

OptionsScreenFontOEM	Sets the screen font to be the standard OEM font

OptionsScreenFontOther	Starts a dialog that allows the user to select any screen font

OptionsScreenFontSystem	Sets the screen font to be the standard non-proportional system font

OptionsToggleInsertMode 	Switches between insert and overwrite modes

OptionsToggleLineNumbers 	Turns line numbering on or off in the current window

OptionsToggleStatusBar	Makes the status bar visible or invisible

OptionsToolbarBottom 	Positions the tool bar at the bottom of the screen

OptionsToolbarFloat	Makes the tool bar into a detached floating window

OptionsToolbarHide	Makes the tool bar invisible

OptionsToolbarLeft 	Positions the tool bar at the left of the screen

OptionsToolbarRight	Positions the tool bar at the right of the screen

OptionsToolbarShow	Makes an invisible tool bar visible at its previous location

OptionsToolbarTop	Positions the tool bar at the top of the screen

TemplateFileAttach	Attaches a template file so the templates within it can be used

TemplateFileCreate	Creates a new, empty template file

TemplateFileDetach 	Detaches an attached template file

TemplateFileSave	Saves an altered template file to disk

TemplateDelete	Deletes a template from a template file

TemplateEdit 	Edits a template from within a template file

TemplateFindMark	Searches in a forward direction from the position of the cursor for the next occurrence of a template marker

TemplateInsert	Inserts a template from a template file into the current file at the position of the cursor

TemplateInsertMark	Inserts a template marker into a template

TemplateNew 	Creates a new empty window suitable for editing a template

TemplateStore	Stores a template in a template file

TemplateStoreAs	Stores a template in a template file, allowing its name to be changed

WindowArrangeIcons 	Arranges all iconized windows neatly

WindowCascade	Arranges all non-iconic windows in a cascade

WindowClose	Closes the current window

WindowDuplicate	Makes an exact duplicate of the current window

WindowIconizeAll	Makes all existing windows iconic

WindowMaximize	Maximizes the current window

WindowNext	Switches control to the next non-iconic window

WindowRestore	Restores the current window from iconized or maximized state

WindowTileHorizontal	Arranges all non-iconic windows in a tile pattern, maximizing their depth

WindowTileVertical	Arranges all non-iconic windows in a tile pattern, maximizing their width

WindowWiden	Adjusts the size and position of the current window to make it as wide as possible


 Default Key Mappings

These tables display the functions that are mapped to certain keys by default. For a description of the action of each function, consult the Functions Reference.

Function Keys

KEY	Used Alone	With Shift	With Ctrl
F1
F2	EditFind	EditRepeatLastFind
F3	EditReplace	EditRepeatLastReplace
F4	TemplateFindMark	WindowTileHorizontal
F5	EditGotoLine	WindowCascade
F6	TemplateInsertMark
F7	ExecRecordPlay	ExecRecordStart	ExecRecordStop
F8
F9	TemplateInsert
F11	ExecDOSCommand	ExecLaunchApp	ExecDOSPrompt
F12	ExecLaunchWindowsTool	ExecConfigureWindowsTools
Movement Keys

For these keys, the default mapping is such that adding Shift to the combination causes a selection to be extended

KEY	Used Alone	With Shift	With Ctrl	With Ctrl+Shift
Up	CaretUp	CaretUpSelect
Down	CaretDown	CaretDownSelect
Left	CaretLeft	CaretLeftSelect	CaretLeftWord	CaretLeftWordSelect
Right	CaretRight	CaretRightSelect	CaretRightWord	CaretRightWordSelect
PgUp	CaretPageUp	CaretPageUpSelect
PgDn	CaretPageDown	CaretPageDownSelect
Home	CaretHome	CaretHomeSelect	EditGotoStart	EditGotoStartSelect
End	CaretEnd	CaretEndSelect	EditGotoEnd	EditGotoEndSelect
Control Keys

KEY	Used Alone	With Shift
Ctrl+C	EditCopy
Ctrl+G	EditGotoLine
Ctrl+K	EditDeleteToEndOfLine	EditDeleteLine
Ctrl+N	FileNew
Ctrl+O	FileOpen	EditSplitLine
Ctrl+P	FilePrint
Ctrl+S	FileSave
Ctrl+T	EditTextTransposeCharacters
Ctrl+V	EditPaste
Ctrl+W	WindowSelect
Ctrl+X	EditCut
Other Keys

KEY	Used Alone	With Shift	With Ctrl
Enter	EditNewline
BackSpace	EditDeleteBackwards
Del	EditDeleteForwards	EditCut
Ins	OptionsToggleInsertMode	EditPaste	EditCopy
Keypad 5	EditCancelSelection


ABEL-HDL Source Reference
Text Editor, Report Viewer, and ABEL-HDL Help

You can create and edit text-based sources with the Text Editor, such as ABEL-HDL behavioral sources.

  Menus

  ABEL-HDL Language Syntax

See Also

  Chapter 4, ABEL-HDL Design


ABEL Syntax Reference
ABEL-HDL Language Syntax Reference

This reference contains detailed information about each of the language elements in ABEL-HDL.  This reference assumes you are familiar with basic ABEL-HDL syntax.  Each entry contains the following sections, if applicable:

Syntax	The required syntax for the element.

Use	A discussion of the potential uses of the element, including any considerations you need to address when using the element.

Examples	Examples of the element, as used in a design description.

See Also	References to other elements and discussions, and to design examples that demonstrate the use of the element.

ABEL-HDL Keywords

.ext - Dot Extensions

= - Constant Declarations

@Directives

Async_reset

Case

Declarations

Device

End

Equations

Functional_block

Fuses

Goto

If-Then-Else

Interface (top module)

Interface (submodule)

Istype

Library

Macro

Module

Node

Pin

Property

State (Declaration)

State (In State_Diagram)

State_Diagram

State_register

Sync_reset

Test_Vectors

Title

Trace

Truth_Table Keyword

When-Then-Else

With

XOR_Factors


=  Constant Declarations

Syntax	id [,id]...  = expr [,expr]...  ;

id	The id is an identifier that names a constant to be used within a module.

expr	The expr is an expression that defines the constant value.

Use	A constant declaration defines constants used in a module.

Note:  The equal sign (=) used for constant declarations in the Declarations section is also used for equations in the Equations section.  See Operators.

The identifiers on the left side of the equals sign are assigned the values listed on the right side.  There is a one-to-one correspondence between the identifiers and the listed expressions.  There must be one expression for each identifier.

The ending semicolon is required after each declaration.

Constants are useful when a value is repeated many times in a module, especially when the value may be changed during the design process.  Rather than changing the value throughout the module, the value can be changed once in the declaration of the constant.

Constant declarations may not be self-referencing; for example:

X = X;

will cause errors, as will the declarations

a = b;
b = a;

An include file, constants.inc, is supplied with ABEL and contains definitions for the most frequently used ABEL-HDL constants.  This file may be included in your design with the command:

Library 'constants' ;

Examples

ABC = 3 * 17;         " ABC is assigned the value 51
Y = 'Bc' ;            " Y = + H4263 ;
X =.X.;               " X means 'don't care'
ADDR = [1,0,15];      " ADDR is a set with 3 elements
 A,B,C = 5,[1,0],6;   " 3 constants declared here

D pin 6;              " see next line
E = [5 * 7,D];        " signal names can be included
G = [1,2]+[3,4];      " set operations are legal
A = B & C;            " operations on identifiers are valid
A = [!B,C];           " set and identifiers on right

See Also

Using Intermediate Expressions


Using Intermediate Expressions

You can use intermediate (constant) expressions in the declarations section to reduce the number of output pins required to implement multi-level functions.  Intermediate expressions can be useful when a module has repeated expressions.  In general, intermediate expressions

~	decrease the number of output pins required, but

~	increase the amount of logic required per output

A constant expression is interpreted by the ABEL compiler as a string of characters, not as a function to be implemented.  For example, for the following sets of Declarations and Equations

Declarations
  TMP1 = [A3..A0] == [B3..B0];
  TMP2 = [A7..A4] == [B7..B4];

Equations
  F = TMP1 & TMP2;

the compiler directly substitutes the declarations into the equations, creating

F = (A7 !$ B7) & (A6 !$ B6) & (A5 !$ B5)
  & (A4 !$ B4) & (A3 !$ B3) & (A2 !$ B2)
  & (A1 !$ B1) & (A0 !$ B0);

In contrast, if you move the constant declarations into the equations section, in the following manner:

Declarations
  TMP1,TMP2 pin 18,19

Equations
  TMP1 = [A3..A0] == [B3..B0];
  TMP2 = [A7..A4] == [B7..B4];
  F = TMP1 & TMP2;

the compiler implements the equations as three discrete product terms.  This will produce the following result:

TMP1 =(A3 !$ B3) & (A2 !$ B2) & (A1 !$ B1) & (A0 !$ B0);

TMP2 =(A7 !$ B7) & (A6 !$ B6) & (A5 !$ B5) & (A4 !$ B4);

F = TMP1 & TMP2;

The first example (using intermediate expressions) requires one output with 16 product terms.  The second example (using equations) requires three outputs with less than 8 product terms per output.  In some cases, the number of product terms required for both methods can be reduced during optimization.

Note:  An alternate method for specifying multi-level circuits such as this is to use the @CARRY  directive.

See Also

Declarations

Equations

Special Constants


Async_reset and Sync_reset

Syntax	SYNC_RESET symbolic_state_id : input_expression ;
ASYNC_RESET symbolic_state_id : input_expression ;

Purpose	In symbolic state descriptions, the SYNC_RESET and ASYNC_RESET statements specify synchronous or asynchronous state machine reset logic in terms of symbolic states.

Use	symbolic_state_id	an identifier used for reference to a symbolic state

input_expression	any valid expression

Examples

ASYNC_RESET Start : Reset ;

SYNC_RESET Start : Reset ;

See Also

State

State_diagram

Using Symbolic State Descriptions


Case Keyword

Syntax	CASE [ expression : state_exp; ]
     [ expression : state_exp; ]
     [ expression : state_exp; ]
               :
ENDCASE ;

Use	The CASE statement is used under the State_diagram section to indicate the transitions of a state machine when there are multiple possible conditions that affect the state transitions.

You can nest Case statements with If-Then-Else, Goto, and other Case statements, and you can use equation blocks.

Examples

case a == 0 : 1 ;
     a == 1 : 2 ;
     a == 2 : 3 ;
     a == 3 : 0 ;
endcase ;

See Also

State_Diagram

Goto

If-Then-Else

With


Declarations Keyword

Syntax	DECLARATIONS
declarations

Use	A declaration is any valid declaration given after the Declarations keyword.  Declarations can be declared in any part of the ABEL-HDL source file.

Example

module andor

  A,B      pin 1,2;   "declarations keyword implied
  Out1     pin 15 istype 'com';

Equations
  Out1 = A & B;

Declarations          "declarations keyword required
  C,D,E,F  pin 3,4,5,6;
  Out2     pin 16 istype 'com';
  Temp1 = C & D;
  Temp2 = E & F;

Equations
  Out2 = Temp1 # Temp2;

end;


Device Keyword

Syntax	device_id DEVICE real_device ;

device_id	An identifier used for the programmer to load filenames

real_device	A string describing the architecture name of the real device represented by device_id.  Only supported devices can be specified.

Use	The device declaration is optional.  It associates the device name used in a module with an actual programmable logic device on which designs are implemented.  Device identifiers used in device declarations should be valid filenames since JEDEC files are created by appending the extension .jed to the identifier.  The ending semicolon is required.

Example

D1 DEVICE 'P16R4' ;


END Keyword

Syntax	END [module_name]

Use	The END statment is paired with the MODULE statement.  See the help section on MODULE for more information.

Example	end source


Equations Keyword

Syntax	EQUATIONS
element [?]:= condition ;
element [?]= condition ;

Use	The equations statement defines the beginning of a group of equations associated with a device.  Equations specify logic functions with Boolean algebra.  An ending semicolon is required after each equation.  The equations following the equation statement are any valid ABEL equations as described in Chapter 2, "Language Structure," of the ABEL-HDL Reference Manual.

Use When-then-else for conditional expressions in equations.  If-then-else is used only in State_diagram descriptions.

CAUTION:  The := and ?:= assignment operators are used only when writing pin-to-pin registered equations.  Use the = and ?= assignment operators for registered equations using detailed dot extensions.

Examples

equations
    A     = B & C # A ;
    [W,Y] = 3         ;
    !F    = B == C    ;
    output.D = in1 # in2 ;

See Also

Module

State_Diagram

Truth_Table

When-Then-Else


Functional_block Keyword

Syntax	DECLARATIONS
instance_name FUNCTIONAL_BLOCK module_name
EQUATIONS
instance_name.port_name = signal_name; :

instance_name	A unique identifer for this instance of the functional block in the current source.

module_name	The name of the lower-level source being instantiated.

port_name	The name of an input or output port from the lower-level source.

signal_name	The signal or signal set by which the ports (inputs and outputs) in the lower-level source are referenced for that instance of the source.

Purpose	You use a functional_block declaration in a top-level ABEL-HDL source to instantiate a declared lower-level source and make the ports of the lower-level source accessible in the top-level source.  You must declare sources with an interface declaration before you instantiate them with a functional_block statement.

Note: The output of an equation must always be on the left side of the equations.

Note:  When a source is instanced by a top-level module, any signal attributes (either explicit or implicit) are inherited by the top-level module signals.  Therefore, you do not need to specify ISTYPEs in top-level sources for instantiated signals.

Creating Multiple Instances

You can use the range operator (..) to instantiate multiple instance names of the source.  For example,

CNT0..CNT3 functional_block cnt4 ;

creates 4 instances of the submodule cnt4.

Mapping Ports to Signals

Signal names are mapped to port names using equations (similar to wiring the signals on a schematic).  You need to specify only the signals used in the top-level source if default values have been specified in the lower-level source interface statement.  See Interface (lower-level source) for more information on setting default values.

To specify the signal wiring, map signal names to the submodule port names with dot extension notation.  There are three kinds of wire: input, output, and interconnect.

Input Wire	Connects submodule outputs to top-level source inputs.

instance.port = input

Output Wire	Connects top-level source outputs to lower-level source inputs.

output = instance.port

Interconnect Wire	Connects the outputs of one instance of a submodule to another instance's inputs.

instance0.port = instance1.port

Examples

module counter;
cnt4 interface (ce, ar, clk -> [q0..q3]); "cnt4's top-level interface declaration.  CNT0..CNT3 functional_block cnt4; "Four instances of cnt4

Clk, AR, CE pin;
Q0..Q3 pin;

equations
  CNT0.[clk,ar,ce]=[Clk,AR,CE]; "Connecting to Clk, AR, and CE inputs.
  [Q0..Q3]   = CNT0.[q0..q3]  ; "Connecting to Q0..Q3 outputs.
end

The figure below shows how the above ABEL-HDL file wires the top-level source's signals to the lower-level source's ports.  Note that the above file instantiates four instances of cnt4, but only one (CNT0) is wired.

Overriding Default Values

You can override the default values given in a lower-level source's interface statement by specifying default equations in the top-level source.  For example, if you have specified a default value of 1 for the signal ce in interface cnt4 but in instance CNT0, you want ce to be 0, you would write:

CNT0.ce = 0 ;

This equation overrides the 1 with a 0.  If you override the default values, you may want to re-optimize the post-linked design.

Unused Outputs (No Connects)

If you do not want to use a submodule's outputs, you can specify them as No Connects (NC) by not wiring up the port to a physical pin.  For example, to make a 3-bit counter out of a 4-bit counter in the top-level module, you might use the following wiring equations:

q2..q0 pin ; "top-level signals
Equations
  [q2..q0] = CNT_A.[q2..q0]

See Also

Hierarchy

Interface - Declare Submodules for Hierarchical Design

Interface (top-level source)

Interface (lower-level source)


Fuses Keyword

Syntax	FUSES
fuse_number = fuse value;
    -or-
fuse_set = fuse value ;

fuse_number 	The fuse number obtained from the logic diagram of a device.

fuse_set	The set of fuse numbers contained in square brackets.

fuse_value	The number indicating fuse(s) states.

Use	The FUSES section of the source file provides a means for explicitly declaring the state of any fuse in the associated device.  Fuse values that appear on the right side of the = symbol can be any number.  If a single fuse number is specified on the left side of the = symbol, the least significant bit (LSB) of the fuse value is assigned to the fuse.  A 0 indicates a fuse intact, and a 1 indicates a blown fuse.  In the case of multiple fuse numbers, the fuse value is expanded to a binary number and truncated or given leading zeros to obtain fuse values for each fuse number.

ABEL-HDL has a limit of 128 fuses per statement, due to set size limitations.

Examples

FUSES
3552 = 1 ;
[3478...3491] = ^Hff;

See Also

Module

Example file orxor.abl

Example file cnt10rom.abl


Goto Keyword

Syntax	GOTO state_exp ;

state_exp	An expression identifying the next state, optionally followed by WITH transition equations.

Use	The GOTO statement causes an unconditional transition to the state indicated by state_exp.  GOTO statements can be nested with If-Then-Else, CASE, and With statements.

Examples

GOTO 0 ; "goto state 0

GOTO x+y ;  "goto the state x + y

See Also

State_Diagram

Case

If-Then-Else

With


If-Then-Else Keyword

Syntax	IF expression THEN state_exp
[ ELSE state_exp ] ;

Chained IF-THEN-ELSE

IF expression THEN state_expression
ELSE IF expression THEN state_expression
ELSE IF expression THEN state_expression
ELSE state_expression ;

expression	Any valid expression.

state_exp	An expression identifying the next state, optionally followed by WITH transition equations.

Use	The IF-THEN-ELSE statement is an easy way to describe the progression from one state to another in a state machine.  The expression following the IF keyword is evaluated, and if the result is true, the machine goes to the state indicated by the state_exp following the THEN keyword.  If the result of the expression is false, the machine advances to the state indicated by the ELSE keyword.

Additional IF-THEN-ELSE statements can be chained to the ELSE clause of an IF-THEN-ELSE statement.  Any number of IF-THEN-ELSE statements can be chained, but the final statement must end with a semicolon.

Note: Equation blocks used within a conditional expression, such as If-Then-Else, result in logic functions that are logically ANDed with the conditional expression that is in effect.

CAUTION: If-Then-Else is only supported within a state_diagram description.  Use When-Then-Else for equations.

Examples

       If A==B then 2 ; "if A equals B goto state 2
       if x-y then j else k; "if x-y is not 0 goto j, else goto k
       if A then b*c; "if A is true (non-zero) goto state b*c

Chained If-Then-Else

if a then 1
  else
if b then 2
  else
if c then 3
  else 0 ;

See Also

State_Diagram

Case

Goto

With


Interface - Declare Modules for Hierarchical Designs
Interface - Declare Lower-level Sources for Hierarchical Designs

The interface keyword is used for hierarchical designs to pass signal names from lower-level sources to the top-level sources that use those signals.  To create a hierarchical design, you need

In the top-level source:

~	An interface declaration for the lower-level source.

~	One or more functional_block statement instantiating the lower-level source for use in the top-level source.

In the lower-level source:

~	An interface declaration of the signals that can be used by top-level sources, and an optional default value for the input signals.

See Also

Hierarchy

Interface (top-level source)

Interface (lower-level source)

Functional_block


Interface Keyword (top-level)

Syntax	module_name INTERFACE (input/set[=value]-> output/set :> bidir/set);

Purpose	The interface keyword declares lower-level modules that are used in the current source and defines the order and default values of their ports (signals).  This declaration is used in conjunction with a functional_block declaration for each instantiation of the lower-level module.

Use	module_name	The name of the lower-level module being declared.

input/set[=value] -> output/set :> bidir/set

A list of signals in the lower-level module.  Signal names are separated with commas.  Use -> and :> to indicate the direction of each port of a functional block.

value	An optional default value for an input that overrides defaults in the lower-level module.

If the lower-level module uses the interface keyword to declare signals, the top-level source interface statement must exactly match the signal listing.

CAUTION:  Interface declarations cannot contain dot extensions.  If you need a specific dot extension across a source boundary (to resolve feedback ambiguities, for example), you must introduce an intermediate signal into the lower-level source to provide the connection to the top-level source.  All dot extension equations for a given output signal must be located in the ABEL-HDL source in which the signal is defined.  No references to that signal's dot extensions can be made outside of the ABEL-HDL source.

Note:  When you instantiate a lower-level source in a top-level source, any signal attributes (either explicit or implicit) are inherited by the top-level source signals that map to the lower-level signals.  Do not specify ISTYPEs for instantiated signals.

Examples

module top;
cnt4 interface (ce,ar,clk -> [q3..q0])

Map port names to signal names with equations.  See Functional_block.

See Also

Hierarchy

Functional_block

Interface (lower-level source)

Interface - Declare Submodules for Hierarchical Designs


Interface Keyword (lower-level)
Interface Keyword (lower-level source)

Syntax	MODULE module_name
INTERFACE (input/set[=value] -> output/set [:> bidir/set]);

module_name	The standard module statement for the ABEL-HDL source.

signal/set	Signals or sets in the lower-level module used as ports to top-level modules.  Use -> and :> to indicate the direction of each port of a functional block.  Use commas to separate groups of signals

value	The default value for the port for input signals only.  Default values do not apply to output and bidirectional signals.

Purpose	The interface declaration is optional for lower-level modules.  Use the interface declaration in lower-level modules to assign a default port list and input values for the module when instantiated in top-level ABEL-HDL sources.  If you use the interface statement in an instantiated module, you must declare the signals and sets in the top-level source in the same order and grouping as given in the interface statement in the lower-level module.

Declaring signals in the lower-level module, although optional, does allow the compiler to check for signal declaration mismatches and therefore reduces the possibility of wiring errors.

Declared Signals

Declared signals can be a list of lower-level pins, sets or a combination of both.  The following constraints apply to the different signal types:

Signal Type	Constraints

Input	Default values must be binary if applied to an individual bit, or any positive integer applied to a set.  All inputs must be listed.

Output	Unlisted outputs are interpreted as No connects (NC).  Unlisted, fed-back outputs are interpreted as nodes in the top-level source following the naming convention
instance_name/node_name

Bidirectional	Listing bidirectional signals is optional, except for those with output enable (OE).  If you specify bidirectional signals, the compiler checks for invalid wire connections.

CAUTION:  Interface declarations cannot contain dot extensions.  If you need a specific dot extension across a source boundary (to resolve feedback ambiguities, for example), you must introduce an intermediate signal into the lower-level source to provide the connection to the top-level source.  All dot extension equations for a given output signal must be located in the ABEL-HDL source in which the signal is defined.  No references to that signal's dot extensions can be made outside of the ABEL-HDL source.

Note:  When you instantiate a lower-level source in a top-level source, any signal attributes (explicit or implicit) are inherited by the top-level source signals that map to the lower-level signals.  Do not specify ISTYPEs for instantiated signals.

Unlisted Signals

If you do not list some signals of the lower-level module in the interface statement, the following rules apply:

Unlisted Pins Are:	The Compiler Interprets Them As:

Inputs or Bidirectionals with OE	Errors

Outputs	No Connects (NC), and they can be removed

Feedback outputs	Nodes in the top-level source, following the naming convention:
instance_name/node_name

Examples

The following interface statement declares inputs ce, ar, and clk, (giving default values for two of them) and outputs q3 through q0.

module cnt4 interface (ce=1,ar=1,clk -> [q3..q0]) ;

Specifying default values allows you to instantiate cnt4 without declaring the ce and ar inputs in the top-level source.  If you do not declare these inputs, they are replaced with the constants 1 and 0, respectively.  Since these constants may affect the optimization, you may need to re-optimize the lower-level source with the constants.

Note:  Supported default values are 1, 0, or X (don't care).  You can  give default values for a set with a positive integer, and each digit of the integer's binary form supplies the default value for the corresponding signal in the set.

See Also

Hierarchy

Functional_block

Interface (top-level source)

Interface - Declare Lower-level Sources for Hierarchical Designs


Library Keyword

Syntax	LIBRARY 'name'

name	A string that specifies the name of the file, excluding the file extension.

Use	The LIBRARY statement causes the contents of the indicated file to be inserted in the ABEL source file.  The insertion begins at the point where the LIBRARY statement is located.  The file extension of '.inc' is appended to the name specified, and the resulting file name is searched for.  If no file is found, ABEL will attempt to find the file in the abel5lib.inc library file.

See Also

Module


Macro Keyword

Syntax	macro_id MACRO [ ( dummy_arg[,dummy_arg]...  ) ] {block} ;

macro_id 	An identifier naming the macro.

dummy_arg	A dummy argument.

block	A block.

Use	The macro declaration statement defines a macro.  You can use macros to include ABEL code in a source file without typing or copying the code everywhere you need it.  A macro is defined once in the declarations section of a module and then used anywhere within the module as frequently as needed.  Macros can be used only within the module in which they are declared.

Examples

The dummy arguments used in the declaration of the macro allow different actual arguments to be used in the macro each time it is invoked in the module.  Within the macro, dummy arguments are preceded by a "?" to indicate that an actual argument will be substituted for the dummy by the ABEL compiler.

D = NAND3 (Clock,Hello,Busy)  ;

brings the text in the block associated with NAND3 into the code, with Clock substituted for ?A, Hello for ?B, and Busy for ?C.  This results in

D = ! (  Clock  &  Hello  &  Busy  )  ;

which is the three input NAND.

See Also

Arguments and Argument Substitution

Declarations

Example file mac.abl


Module Keyword

Syntax	MODULE modname [ ( dummy_arg [,dummy_arg] ...   ) ]

modname	A valid identifier naming the module.

dummy_arg 	A dummy argument.

Use	The module statement defines the beginning of a module and must be paired with an END statement that defines the module's end.

See Also

End

Interface (submodule)

Arguments and Argument Subsitution

Supported ASCII Characters

Identifiers


Node Keyword

Syntax	[!]node_id[,[!]node_id...] NODE [node#s...] [ISTYPE 'attr'];

node_id 	An identifier used for reference to a node in a logic design.

node #s 	The node number on the real device.

attr 	A string that specifies node attributes  for devices with programmable nodes.

Use	The NODE keyword is used to declare those signals that may be assigned to buried nodes within a device.

Example

The node attribute string, Istype 'attr', specifies node attributes.   The node declaration,

B NODE istype 'reg' ;

specifies that node B is a buried flip-flop.

a0..a3 node 22..25;

Assigns a0, a1, a2, and a3 to nodes 22, 23, 24, and 25, respectively.

See Also

Istype

Pin

Module

Pin-to-Pin Designs


Options Keyword

The options keyword is not supported.  Set processing options in the Properties dialog box.


Pin Keyword

Syntax	[!]pin_id[,[!]pin_id...] PIN [pin#[,pin#]] [ISTYPE 'attr'];

pin_id	An identifier used to refer to a pin throughout a module.

pin#	The pin number on the real device.

attr	A string that specifies pin attributes  for devices with programmable pins.

Use	The PIN keyword is used to declare those input and output signals that must eventually be available on a device I/O pin.  You should also specify pin attributes for all pins used as outputs.

When lists of pin_ids and pin #s are used in one pin declaration statement, there is a one-to-one correspondence between the identifiers and numbers given.  If you declare pin numbers, you must include numbers for each identifier listed in the statement.

Example

!Clock, Reset, S1 PIN 12,15,3;

This pin declaration assigns the pin name, Clock to pin 12; Reset to pin 15; and S1 to pin 3.

The use of the "!' operator in pin declarations indicates that the pin is active-low and will be automatically negated when processed by the language processor.

Errors

The following are pin assignment errors that cause errors in ABEL:

1.	Assigning the same pin number to two signals (A1, A0 pin 17,17;).

2.	Assigning invalid pin numbers when a device has been specified (Q3 pin 28 in a 20 pin device).  The fitter for a device can optionally correct invalid pin assignments.

See Also

Istype

Node

Module

Pin-to-pin vs. Detailed Descriptions for Registered Designs


Property Keyword

Syntax	property_id PROPERTY 'string' ;

Use	The PROPERTY declaration statement allows you to specify additional design information associated with an external processing module (such as a specialized device kit).

The property_id is used to identify properties relevant to specific external modules, and the string argument contains the actual property data.

CAUTION:  Property_ID's and strings may be case-sensitive.  Check your device kit documentation.

See Also

Example file amd_cm8.abl


State Keyword (Declaration)

Syntax	state_id [, state_id ...] STATE [IN statereg_id ]

Purpose	The State declaration is made to declare a symbolic state name, and optionally associate it with a state register.

Use	state_id	A symbolic state name to be referenced in a symbolic state description.

statereg_id	An identifier for a state register.

If your design includes more than one symbolic state machine, use the IN keyword to associate each state with the corresponding state register.

Each state you declare corresponds to one flip-flop in a one-hot state machine.

See Also

Async_reset/Sync_reset

State_register

Using Symbolic State Descriptions


State Keyword (in State_diagram)

Syntax	[STATE state_exp : [equation]
[equation]
  :
  :
trans_stmt ; ...]

Purpose	The state keyword and the associated section describes one state of a state diagram.  It includes a state value (or symbolic state name), a state transition statement, and optional state output equations.

Use	state_exp	An expression, value, or symbolic state name giving the current state.

equation	A valid equation that defines the state machine outputs.

trans_stmt	IF-THEN-ELSE, CASE, or GOTO statements, optionally followed by WITH transition equations.

The specification of a state description requires the use of the State_diagram syntax (which defines the state machine) and the If-Then-Else, Case, Goto, and With-endwith statements (which determine the operation of the state machine).  Symbolic state machines (machines for which the actual state registers and state values are unspecified) require additional declarations for the symbolic state register and state names.

An ending semicolon is required after each transition statement.

See Also

Async_reset and Sync_reset

Using Symbolic State Descriptions

Case

Goto

If-then-else

Module

State (Declaration)

State_diagram

Truth_table

With


State_diagram Keyword

Syntax	STATE_DIAGRAM state_reg
          [-> state_out]
   STATE state_exp : [equation]
                     [equation]
                         :
                         :
                      trans_stmt ;]

state_reg	An identifier or set of identifiers specifying the signals that determine the current state of the machine.

state_out 	An identifier or set of identifiers that determine the next state of the machine (for designs with external registers).

state_exp 	An expression giving the current state.

equation	A valid equation that defines the state machine outputs.

trans_stmt	An IF-THEN-ELSE, CASE, or GOTO statement, optionally followed by WITH transition equations.

Use	The state description describes the operation of a sequential state machine implemented with programmable logic.  You can use state descriptions to describe logic as an alternative to Boolean equations or truth tables.

Example

The following is an example of a simple state machine that advances from one state to the next, setting the output to the current state, and then starting over again.  Note that the states do not need to be specified in any particular order.  Note also that state 2 is identified by an expression rather than by a constant.  The state register is composed of the signals a and b.

state_diagram [a,b]

state 3: y = 3 ;
        goto 0 ;

state 1: y = 1 ;
        goto S2 ;

state 0: y = 0 ;
        goto 1 ;

state S2; y = S2 ;
         goto 3 ;

See Also

Equations

Equation Blocks

Truth_Tables

Module

Case

If-Then-Else

Goto

With


State_register Keyword

Syntax	statereg_id STATE_REGISTER ;

Purpose	For symbolic state diagrams, State_register declares a symbolic state machine name.

Use	statereg_id	An identifier naming the state_register.

See Also

State (Declarations)

State_diagram

Using Symbolic State Descriptions


Test_vectors Keyword

Syntax	TEST_VECTORS [note]
(inputs   -> outputs   )
 invalues -> outvalues ;
...

note	A string used to describe the test vectors.

inputs	An identifier or set of identifiers specifying the names of the input signals to the device, or feedback output signals.

outputs	An identifier or set of identifiers specifying the output signals from the device.

invalues	An input value or set of input values.

outvalues	An output value or set of output values resulting from the given inputs.

Use	Test vectors specify the expected functional operation of a logic device by explicitly defining the device outputs as functions of the inputs.  Test vectors are used for simulation of an internal model of the device and for functional testing of the programmed device.

Examples

Following is a simple test vector table:

TEST_VECTORS
    ( [A,B] -> [C,D] )
      [0,0] -> [1,1] ;
      [0,1] -> [1,0] ;
      [1,0] -> [0,1] ;
      [1,1] -> [0,0] ;

The following test vector table is equivalent to the table specified above because values for sets can be specified with numeric constants.

TEST_VECTORS
    ( [A,B] -> [C,D] )
       0    ->  3 ;
       1    ->  2 ;
       2    ->  1 ;
       3    ->  0 ;

If the signal identifiers in the test vector header were declared as active-low in the declaration section, then constant values specified in the test vectors will be inverted accordingly.

See Also

Module


Title Keyword

Syntax	TITLE 'string'

Use	The title statement is used to give a module a title that will appear as a header in both the programmer load file and documentation file created by the language processor.  The title is specified in the string following the keyword, TITLE.  The string is opened and closed by an apostrophe.  The title statement is optional.

Examples	An example of a title statement that spans three lines and describes the logic design is shown below:

module m6809a
title '6809 memory decode, Jean Designer
       Data I/O Corp Redmond WA'

See Also

Module


Trace Keyword

Syntax	TRACE (inputs -> outputs) ;

Use	The TRACE statement is used to control the display features of the PLASim and JEDSim simulation modules.  TRACE statements can be placed before a test vector section, or imbedded within a sequence of test vectors.

Example

TRACE           (  [A,B] -> [C  ]  );
TEST_VECTORS    (  [A,B] -> [C,D]  )
                     0   ->   3     ;
                     1   ->   2     ;
TRACE           (  [A,B] -> [  D]  );
                     2   ->   1     ;
                     3   ->   0     ;

See Also

Test_vectors


Truth_Table Keyword

Syntax	TRUTH_TABLE ( inputs   -> outputs )
              invalues -> outvalues ;
                   or
TRUTH_TABLE ( inputs   :> reg_outs )
              invalues :> reg_outvalues ;
                   or
TRUTH_TABLE ( inputs   :> reg_outs      -> outputs )
              invalues :> reg_outvalues -> outvalues ;

inputs	Input signal names to the logic function.

outputs	Output signal names from the logic function.

reg_outs	Registered (clocked) output signal names.

-> 	Indicates the input to output function for combinational outputs.

:> 	Indicates the input to output function for registered outputs.

Use	Truth tables specify outputs as functions of different input combinations in a tabular form.  Truth tables are another way to describe logic designs with ABEL and may be used in lieu of (or in addition to) equations and state diagrams.  A truth table includes a header describing the format of the table and the table.

See Also

Module

Equations

State_Diagram

@Dcset

@Onset


Istype Keyword

Syntax	signals [PIN | NODE] numbers ISTYPE 'attr';

signal 	A pin or node identifier.

number	Optional pin or node numbers.

attr	A string that specifies attributes for the signals, separated by commas.

Use	The ISTYPE statement defines attributes (characteristics) of signals (pins and nodes).  You should use signal attributes to remove ambiguities in architecture-independent designs.  Even when you have specified a device, using attributes ensures that the design operates consistently if the device is changed later.

You can combine a pin or node declaration with an ISTYPE statement in a single declaration.  Supported attributes are listed below.

Examples

F0, A pin istype 'invert, reg' ;

This declaration statement defines F0 and A as inverted D-type flip-flops.  The following signal declarations are all supported:

q3,q2,q1,q0    NODE   ISTYPE 'reg_SR';
Clk,a,b,c      PIN    1,2,3,4;
reset          PIN;
reset          ISTYPE 'com';
Output         PIN 15    ISTYPE 'reg,invert';

Istype Attributes

'buffer' 	Non-inverted signal

'collapse' 	Collapse (remove) this signal.

'com' 	Combinational signal

'dc' 	Unspecified logic is don't care.

'invert' 	Inverted signal

'keep' 	Do not collapse this signal from equations.

'neg' 	Unspecified logic is 1.

'pos' 	Unspecified logic is 0.

'reg' 	Registered output signal

'reg_D' 	Registered output signal for D Flip-flop

'reg_G' 	Registered gated clock memory element

'reg_JK' 	JK-type registered output signal

'reg_SR' 	SR-type registered output signal

'reg_T' 	T-type registered output signal

'retain'	Do not minimize this output.  Preserve redundant product terms.

'xor' 	XOR gate

See Also

Dot Extensions

Node

Pin


Istype 'buffer' - Non-inverter attribute

Syntax	signal_name [,signal_name] [PIN|NODE] ISTYPE 'buffer' ;

Use	Signal attribute 'buffer,' (along with its counterpart, 'invert,' to control output inversion) enforces the existence or non-existence of a hardware inverter at the device pin associated with the specified output signal.  This is important because the state of the inverter affects a register's reset, preset, preload, and powerup behavior (as observed on the associated output pin).

The 'buffer' attribute indicates that the target architecture does not have an inverter between the associated flip-flop (if any) and the actual output pin.

Examples

q0,q1,q2   pin  istype 'buffer';
a0,a2           istype 'buffer';

See Also

'invert'

Using Istype 'buffer' and 'invert


Istype 'collapse' - Collapse Combinational Node Attribute

Syntax	signal_name [,signal_name] [PIN|NODE] ISTYPE 'collapse' ;

Use	Signal attribute 'collapse' indicates that this combinational node can be collapsed (removed).  The opposite attribute is ISTYPE 'keep'.

Example	In the following example, signal b is given the 'collapse' attribute:

module coll_b
a,c,d,e   pin ;
b         pin istype 'collapse'

equations
a = b & e;
b = c & d;

end

The resulting equation collapses b out of the equations:

a = c & d & e ;

See Also

'keep'


Istype 'com' - Combinational Signal Attribute

Syntax	signal_name [,signal_name] [PIN|NODE] ISTYPE 'com' ;

Use	Signal attribute 'com' is used to specify that a signal has no register element associated with it or that any register should be bypassed.

See Also

'reg'


Istype 'dc' - Unspecified Logic is Don't Care

Syntax	signal_name [,signal_name] [PIN|NODE] ISTYPE 'com' ;

Use	Signal attribute 'dc' is used to specify that unspecified logic should be given a value of don't care.

The 'dc' attribute is equivalent to the @DCSET directive, except that it operates on individual signals instead of on an entire section of a design.

Note:  'dc,' 'neg,' and 'pos' are mutually exclusive.

Caution:  The @DCSET directive overrides 'dc,' 'neg,' and 'pos'.

See Also

'neg'

'pos'

'buffer'

'invert'

'xor'


Istype 'invert' - Inverter Attribute

Syntax	signal_name [,signal_name] [PIN|NODE] ISTYPE 'invert' ;

Use	Signal attribute 'invert', along with its counterpart, 'buffer,' controls output inversion, enforcing the existence or non-existence of a hardware inverter at the device pin associated with the specified output signal.

In registered devices, the 'invert' attribute ensures that an inverter will be located between the output pin and its associated register output.  This is important because the location of the inverter affects a register's reset, preset, preload, and powerup behavior (as observed on the associated output pin).

See Also

'buffer'

Using Istype 'buffer' and 'invert


Istype 'invert' and 'buffer'
Using Istype 'invert' and 'buffer'

The istype 'invert' declaration ensures an inverter between the signal's output pin and its associated flip-flop.  The istype 'buffer' declaration ensures no inverter between the flip-flop and pin.  These attributes are primarily used to control the behavior of presets, resets, and power-up states for devices with programmable output pin inversion, and to restrict device-independent designs to certain classes of parts (only those with inverted outputs, for example).

An output can be declared as type 'invert', and still be implemented with either positive or negative-polarity.  This is because many devices (such as the P16V8, P16RP4, and others) feature fixed inverters between the flip-flop outputs and the actual output pins, and programmable-polarity elements located at the terminus of the programmable arrays (before the flip-flops).  Devices such as this allow automatic polarity selection to be performed (to reduce product term requirements) without affecting the behavior of flip-flops (as observed on the device outputs).

Since the 'invert' and 'buffer' attributes are related to flip-flops, they have no meaning and do not apply to signals that are used or declared as combinational (for example, by using the 'COM' attribute), nor do they apply to input signals.

When 'invert' or 'buffer' are used for an output signal, the information is passed to later ABEL programs (such as the PLASim simulator, device fitters, and the Fuseasm fuse mapper) in the OPEN-ABEL file.  If the 'invert' attribute is specified, outputs that were described using the dot extensions .D, .T, .S, .R., .J., and .K are complemented in the programmed device.

To see two designs that illustrate this concept, click on "Invert/Buffer Example" below.

Invert/Buffer Example

The .Q dot extension (for feedback specification) is directly affected by the 'invert' and 'buffer' attributes.  When 'invert' is specified, the .Q feedback reference is always the complement of the .FB feedback reference.  When 'buffer' is specified, .Q and .FB feedback references are synonymous.

See Also

Feedback - .Q and .FB


Invert/Buffer Example

The test vectors in the following two designs illustrate how the 'invert' attribute complements output signals with detailed dot extensions (.D, .T, .S, .R., .J., and .K).

module buffer
      q0,q1 pin istype 'reg,buffer';
      clock pin;
      reset pin;

equations
      [q1,q0].clk = clock;
      [q1.D,q0.D] = [q1.Q,q0.Q] + 1;
      [q1.SR,q0.SR] = reset;

test vectors
   ([clock,reset]->[q1,q0])
    [ .c.  ,  1  ]->[ 0, 0];
    [ .c.  ,  0  ]->[ 0, 1];
    [ .c.  ,  0  ]->[ 1, 0];
    [ .c.  ,  0  ]->[ 1, 1];
    [ .c.  ,  0  ]->[ 0, 0];
    [ .c.  ,  0  ]->[ 0, 1];
    [ .c.  ,  1  ]->[ 0, 0];
end

module invert
      q0,q1 pin istype 'reg,invert';
      clock pin;
      reset pin;

equations
     [q1,q0].clk = clock;
     [q1.D,q0.D] = ([q1.Q,q0.Q] + 1);
     [q1.SR,q0.SR] = reset;

test vectors
   ([clock,reset]->[q1,q0])
    [ .c.  ,  1  ]->[ 1, 1];
    [ .c.,   0  ]->[ 1, 0];
    [ .c.  ,  0  ]->[ 0, 1];
    [ .c.  ,  0  ]->[ 0, 0];
    [ .c.  ,  0  ]->[ 1, 1];
    [ .c.  ,  0  ]->[ 1, 0];
    [ .c.  ,  1  ]->[ 1, 1];
end

The 'invert' declaration in the second design results in inverted outputs and in an inverted reset function.


Istype 'keep' - Do Not Collapse Signal

Syntax	signal_name [,signal_name] [PIN|NODE] ISTYPE 'keep' ;

Use	Signal attribute 'keep' indicates that the combinational node should not be collapsed (removed).

See Also

'collapse'


Istype 'neg' - Unspecified Logic is 1

Syntax	signal_name [,signal_name] [PIN|NODE] ISTYPE 'neg' ;

Use	Signal attribute 'neg' indicates that unspecified logic should be given the value of 1.

Note:  The 'neg' or 'pos' attribute is implied if a device is specified.  For example, 'neg' is implied if the device output is inverted (for example, with a 16L8).

Caution:  The @DCSET directive overrides 'dc,' 'neg,' and 'pos'.

Note:  'dc,' 'neg,' and 'pos' are mutually exclusive.

See Also

'dc'

'pos'

'buffer'

'invert'

'xor'


Istype 'pos' - Unspecified Logic is 0

Syntax	signal_name [,signal_name] [PIN|NODE] ISTYPE 'pos' ;

Use	Signal attribute 'pos' indicates that unspecified logic should be given the value of 0.

Note:  The 'neg' or 'pos' attribute is implied if a device is specified.  For example, 'pos' is implied if the device output is not inverted.

Caution:  The @DCSET directive overrides 'dc,' 'neg,' and 'pos'.

Note:  'dc,' 'neg,' and 'pos' are mutually exclusive.

See Also

'dc'

'neg'

'buffer'

'invert'

'xor'


Istype 'reg' - Clocked Memory Element

Syntax	signal_name [,signal_name] [PIN|NODE] ISTYPE 'reg' ;

Use	Signal attribute 'reg' indicates that the associated signal has a D-type flip-flop as its memory element.  Since flip-flop types are normally determined by the use of ':=' or by the use of dot extensions (.D, .T, etc.) in equations, the 'reg' attribute is only significant when state diagrams are used.  When 'reg' is specified, the equations resulting from an ABEL-HDL state diagram will be pin-to-pin registered equations (the same as if you had written equations using ':=').  You do not need to worry about the existence of inverted output pins.

See Also

'buffer'

'reg_SR'

'invert'

'reg_T'

'neg'

'xor'

'reg_D'

Istype

'reg_G'

'reg_JK'


Istype 'reg_D' - D Flip-flop Clocked
Istype 'reg_D' - D Flip-flop Clocked Memory Element

Syntax	signal_name [,signal_name] [PIN|NODE] ISTYPE 'reg_d' ;

Use	Signal attribute 'reg_d' indicates that the associated signal has a D-type flip-flop as its memory element.  When 'reg_D' is specified, equations generated from an ABEL-HDL state diagram will assume a D-type register.  If this attribute is specified; however, you will need to specify the 'invert' or 'buffer' attribute to ensure consistent operation in different architectures.  To eliminate the need for the 'invert' or 'buffer' attributes, use the 'reg' attribute instead of 'reg_D'.

See Also

'buffer'

'reg_SR'

'invert'

'reg_T'

'neg'

'xor'

'reg'

Istype

'reg_G'

'reg_JK'


Istype 'reg_G' - D Flip-flop Gated Clock Memory Element

Syntax	signal_name [,signal_name] [PIN|NODE] ISTYPE 'reg_g' ;

Use	Signal attribute 'reg_G' indicates that the associated signal has a D-type flip-flop with gated clock as its memory element.  Equations generated from an ABEL-HDL state diagram will assume this register type if the 'reg_g' attribute is specified; however, you will need to specify the 'invert' or 'buffer' attribute to ensure consistent operation in different architectures.

See Also

'buffer'

'reg_SR'

'invert'

'reg_T'

'neg'

'xor'

'reg'

'reg_D'

Istype

'reg_JK'


Istype 'reg_JK' - JK Flip-flop Clocked Memory Element

Syntax	signal_name [,signal_name] [PIN|NODE] ISTYPE 'reg_jk' ;

Use	Signal attribute 'reg_jk' indicates that the associated signal has a JK-type flip-flop as its memory element.  Equations generated from an ABEL-HDL state diagram will assume this register type if the 'reg_jk' attribute is specified; however, you will need to specify the 'invert' or 'buffer' attribute to ensure consistent operation in different architectures.

See Also

'buffer'

'reg_SR'

'invert'

'reg_T'

'neg'

'xor'

'reg'

'reg_D'

Istype

'reg_G'


Istype 'reg_SR' - SR Flip-flop Clocked Memory Element

Syntax	signal_name [,signal_name] [PIN|NODE] ISTYPE 'reg_sr' ;

Use	Signal attribute 'reg_sr' indicates that the associated signal has an SR-type flip-flop as its memory element.  Equations generated from an ABEL-HDL state diagram will assume this register type if the 'reg_sr' attribute is specified; however, you will need to specify the 'invert' or 'buffer' attribute to ensure consistent operation in different architectures.

See Also

'buffer'

'reg_JK'

'invert'

'reg_T'

'neg'

'xor'

'reg'

'reg_D'

Istype

'reg_G'


Istype 'reg_T' - T Flip-flop Clocked Memory Element

Syntax	signal_name [,signal_name] [PIN|NODE] ISTYPE 'reg_t' ;

Use	Signal attribute 'reg_t' indicates that the associated signal has a T-type flip-flop as its memory element.  Equations generated from an ABEL-HDL state diagram will assume this register type if the 'reg_t' attribute is specified; however, you will need to specify the 'invert' or 'buffer' attribute to ensure consistent operation in different architectures.

See Also

'buffer'

'reg_SR'

'reg_JK'

'invert'

'neg'

'xor'

'reg'

'reg_D'

Istype

'reg_G'


Istype 'retain' - Do Not Minimize This Output

Syntax	signal_name [,signal_name] [PIN|NODE] ISTYPE 'retain' ;

Use	Signal attribute 'retain' indicates that redundant product terms for this signal should be retained.  The 'retain' attribute only controls optimization performed in the compiler.  To preserve redundant product terms, you must also specify no reduction for optimization and for the device fitting software.


Istype 'xor' - XOR Gate in Target Device

Syntax	signal_name [,signal_name] [PIN|NODE] ISTYPE 'xor' ;

Use	Signal attribute 'xor' indicates that the target architecture has an XOR gate, so one top-level exclusive-OR operator is retained in the design equations.

See Also

'buffer'

'reg_SR'

'reg_JK'

'invert'

'reg_T'

'neg'

'reg'

'reg_D'

Istype

'reg_G'


When-Then-Else Keyword

Syntax 	[ WHEN condition THEN ] [!] element=expression ;
[ ELSE equation ];
    -or-
[ WHEN condition THEN ] equation ;
[ ELSE equation ];

condition	Any valid expression.

element	An identifier naming a signal or set of signals, or an actual set, to which the value of the expression will be assigned.

expression	Any valid expression.

Use	This statement is used in equations.  Equations use the four assignment operators = and ?= (combinational or detailed), and := and ?:= (registered pin-to-pin).

Note: Equation blocks used within a conditional expression such as When-Then-Else result in logic functions that are logically ANDed with the conditional expression that is in effect.

CAUTION: When-Then-Else is only supported in equations.  Use If-Then-Else for state diagrams.

Examples

WHEN B THEN A=B;
ELSE A=C;

WHEN      (Mode == S_Data) THEN  { Out_data := S_in;
                                   S_Valid  := 1;
                                 }
ELSE WHEN (Mode == T_Data) THEN  { Out_data := T_in;
                                   T_Valid  := 1;
                                 }

See Also

Equations

Equation Blocks


With Keyword

Syntax	trans_stmt state_exp WITH { equation
[equation]
}

trans_stmt	The IF, ELSE, or CASE statements.

state_exp	The next state.

equation	An equation for state machine outputs.

Use	The With statement is used in the State_diagram section.  When used in conjunction with the If-then or Case statement, it allows output equations to be written in terms of transitions.

Note:  The endwith keyword is supported for backward compatibility.

Examples

state 5 : IF a == 1 then 1
                    WITH {x := 1 ;
                          y := 1 ;}
          ELSE 2    WITH {x := 0 ;
                          y := 1 ;}

See Also

State_Diagram

Case

Goto

If-Then-Else

Equation blocks


Xor_Factors Keyword

Syntax:	XOR_FACTORS
signal name = xor_factors ;

Use	The XOR_Factor section allows you to specify a Boolean expression that is to be factored out of (and XORed with) the sum-of-products reduced equations.  This can result in dramatic reductions in the size of the reduced equations.  The XOR_Factor feature is a technique for converting a sum of products (SOP) equation into an exclusive OR (XOR) equation.  The resulting equation contains the sum of product functions that, when exclusive ORed together, have the same function as the original.  The XOR_Factor equation will be divided into the original equation, with factor (or its complement) on one side of the XOR and the remainder on the other side.

Examples

For the following equations,

!Q16 =  A &  B &      !D
     #  A &  B & !C
     #      !B &  C &  D
     # !A &       C &  D

a useful XOR_Factor would be

XOR_Factors

Q16 = A & B;


Glossary

Click on the letters below to jump to a letter.

A B C D E F G H I J K L M N O P Q R S T U V W  X  Y  Z

A

Active

Actual Argument

Architecture-independent

ASIC

Attribute

Attribute Values

Attribute Windows

B

Banked

Behavioral Description

Back Annotation

Block

Breakpoints

Bubble

Bus

Bus Expansion

Bus Name

Bus Tap

C

Cell Symbol

Compound Net Name

Constant

Critical Path

D

DeMorgan-Equivalent Gates

Derived Attribute

Device Kit

Detailed

Device-specific

Directive

Dot Extension

Dummy Arguments

E

External Net

F

Fan-In

Fan-Out

Fan-In/Fan-Out Analysis

Fitter

FPGA

G

Gate

Gate Symbol

Global Net Names

H

Hi/Lo Analysis

Hierarchical Design

I

I/O Marker

Identifier

Image Dump

Implicit Net Connections

Instance

Instance Name

Inversion Bubble

Iterated Instances

J

K

L

Label

Local Net

Log File

Logic Diagram Package

M

Master Symbol

Mealy State Machine

Miser Bits

Moore State Machine

N

Net

Net Name

Normalization

Normalized

O

OPEN-ABEL

Operand

Operator

Ordered Bus

Overlapping Condition

P

PAL

Pin

Pin-to-Pin

PLA File

PLD

Polarity

Process

Programmer Load File

Programmable Output Inversion

Programmable-polarity

Project

Properties

Q

Q Feedback

R

S

Scalar Net

Sheet

Signal

Signal Attributes

Simple Net Name

Source

Special Constants

Spike

State Machine

String

Structural Description

Strategy

Symbol

T

Table

Target Device

Transcript

Trigger

Turbo Bits

U

Unordered Bus

User Electronic Signature Word

V

W

X

Y

Z


Active - The window or design file that is currently being worked on is called active. An active window has minimize/maximize buttons and a control menu box displayed on the title bar.


Actual Argument - An actual argument is the argument (value) used in the macro, module or directive.  The actual argument is substituted for the dummy argument.  An actual argument can be any text, including identifiers, numbers, strings, operators, sets, or any other element of ABEL-HDL.


Architecture-independent (also device-independent)- A design that does not rely on specific device features to implement.


ASIC - Application-Specific Integrated Circuit.


Attribute - A characteristic for a component or symbol that adds specific information about the symbol in the netlist which is used by a back-end process. An attribute can be anything from a part number to a propagation delay. A symbol can have up to 200 attributes. The first 100 are reserved for use by the Schematic and Symbol Editors.


Attribute Values

Attributes are assigned default values by the user in the ecs.ini file. Since some attribute values (such as transistor width) might need to modified after simulation, attribute values can be overridden in the Hierarchy Navigator.


Attribute Windows

Attribute values can be displayed next to a symbol. An attribute and its value appears in a window, whose position is specified by the Attribute Location command in Schematic Editor Edit menu. The window is not visible unless a value is displayed in it. An attribute cannot be displayed in a window unless a window number is assigned to that attribute in the ecs.ini file. (An exception is that an attribute without a defined window can be temporarily displayed in another attribute's window.  See your  Schematic Editor Reference for more information.)


Banked - Outputs are banked when more than one output shares the same preset or reset.


Behavioral Description - A circuit description in terms of its logical behavior, using truth tables, equations, or state diagrams.


Back Annotation - The process of writing information into a schematic from an external source.  For example, writing post-route timing information such as delay attributes, or assigning reference designators from an external PCB packager.


Block - A block symbol represents lower-level circuitry. The block does not show any details of the circuitry, except for I/O pins. Blocks are most often used to simplify a complex schematic, or to allow a large schematic to fit on a single sheet. Blocks usually represent repeated sections of circuitry, but can replace any part of a schematic.


Breakpoints - A combination of signal states that are used to indicate when simulation should stop.


Bubble - A bubble is a circle at a gate input or output to show logic inversion. For example, a NOR gate is drawn with a bubble at its output to indicate that "high" inputs produce a "low" output.


Bus - A bus is a named collection of two or more wires or other buses. Attaching a bus tap to a single wire "promotes" the wire to a bus.

In a schematic, a bus looks like a single wire, but is displayed in a different color. (The color does not appear until you name the bus.) The indivdual signals within a bus can be tapped off at any point along the bus, as often as needed. (The Schematic Editor does not check to see if you are overloading the bus.)


Bus Expansion - Expanding a bus into its constituent nets (for example, the bus NetA[0:7] becomes NetA[0], NetA[1],.... NetA[7].


Bus Name - The name given to a group of signals that have been gathered together into a bus (for example SUM[0:15]).


Bus Tap - A single wire attached at right angles to a bus, to "pick off" one signal. Adding a bus tap to a single-wire net "promotes" it to a bus.


Cell Symbol - A primitive symbol representing the lowest functional element of an integrated circuit design (for example, an NMOS transistor).


Compound Net Name - A net name that contains more than one name, effectively creating a bus.


Critical Path - The path through a circuit which determines the maximum speed at which the circuit can operate.


Constant - A declared identifier and associated value that can be used in subsequent language statements.  Constants can be anything from simple numeric values to complex ABEL-HDL logic expressions.   A constant is an identifier that retains a constant value throughout a module.


DeMorgan-equivalent Gates - If two gates are exact inversions of each other -- one has bubbles where the other doesn't, one is AND and the other OR -- then they have the same truth table and are logically equivalent. For example, a NAND gate is equivalent to an OR gate with bubbles on its inputs. Named after the mathematician who first stated the rule.


Derived Attribute - A derived attribute does not have a fixed value.  Its value is calculated from other attribute values and/or other values in a table.


Detailed - A design description that describes how the internal functions of a device operate, and so is limited to devices that contain the internal features referenced.


Device Kit - A device kit is an optional package for The Project Navigator that contains all of the tools you need to create designs for a device or family of devices. Device Kits can contain device synthesis and place and route applications, device-specific  project examples, device-specific schematic libraries, and device optimization and pin assignment software.


Device-specific - A design that references specific device features.  A device-specific design cannot usually be migrated to other device architectures without some modification.


Directive - Directives are special commands in an ABEL-HDL source file that allow you to conditionally include source code, import source code from another file, print messages during processing, and affect the way a source file is processed.  Directives start with the at character (@).


Derived Attribute - An attribute value that is derived from other attribute values using a formula.


Dummy Arguments - Dummy arguments are identifiers used to indicate where an actual argument is to be substituted in a macro, module or directive.


Dot Extension - A special identifer appended to a signal (such as a pin or node) that represents a secondary input to or output from a device macrocell. Secondary signals include such things as clocks (.CLK), flip-flop resets (.AR, .SR and .CLR) and feedback lines (.FB, .Q, and .COM).


External Net - A node or wire in a schematic that contains a connection point that is visible outside the circuit, usually represented by an I/O flag or pin.  The net would have a corresponding pin on the symbol for the schematic.


Fan-In - The load presented by an input. If the total input load is greater than the driving net's capacity, the circuit may work erratically, or not at all.


Fan-Out - The drive capability of a net. If it is less than the total load on the net, the circuit may work erratically, or not at all.


Fan-In/Fan-Out Analysis - The comparison of a net's drive capability to the load attached to the net. If the load is greater than the drive capacity, the circuit may work erratically, or not at all.


Fitter - A program that maps designs into a targeted device.  This process may include assigning pins and nodes, logic synthesis and complex device routing.  See Also Device Kit.


FPGA - Field-Programmable Gate Array. The generic name for a programmable logic circuit that is constructed of smaller blocks, other than traditional PLD sum-of-products macrocells.


Gate - A single logic element, such as an AND gate, NOR gate, or inverter.


Gate Symbol - A primitive symbol representing the lowest-level functional element of a printed circuit board design (for example, an AND gate).


Global Net Names - Names for nets that are available at all levels of a circuit and are assumed to be connected (for example, Vcc and GND).


Hi/Lo Analysis - A fan-in/fan-out analysis that takes into account devices' load and drive characteristics under dynamic conditions. The dynamic characteristics, especially for TTL devices, are not always as good as the static characteristics.


Hierarchical Design - A design with more than one level is said to be "hierarchical". A single-level design is "flat". Converting a section of circuitry to a block makes a flat design hierarchical.

Hierarchy has no relation to the number of schematic sheets. A single-sheet design can be hierarchical, a 20-sheet design flat.


I/O Marker - A flag attached to a pin or wire that shows the name of the bus to which the wire connects, and the "polarity" (in, out, bi-directional) of the pin.


Identifier - A name or label used in a source file to reference input pins, nodes, sets, constants, keywords or output pins.


Image Dump - The copying of all or part of a schematic to the Windows Clipboard. From the Clipboard it can be saved to a file or printed.


Implicit Net Connections - All nets with the same name are implicitly connected, even across schematic sheets.


Instance - An instance is the occurrence of a transistor, IC, or other component in a schematic. A schematic with five 7465 ICs has five "instances" of that part.


Instance Name - Each instance of a symbol has a unique reference designator, its instance name.


Inversion Bubble - A circle at a gate input or output to show logic inversion. For example, a NOR gate is drawn with a bubble at its output to indicate that "high" inputs produce a "low" output.


Iterated Instances - An array of identical symbol instances placed in a schematic and represented with a bracketed instance name (for example, and[0:7] represents 8 instances of the "and" symbol named and[0], and[1]...and[7].


Label - A label is a sequence of alphanumeric characters that does not begin with a number, and is not an ABEL-HDL reserved word (keyword).


Local Net - A node or wire in a schematic that contains only connection points internal to that schematic and is, therefore, not externally accessible.


Log File - A data file with the most-recent changes to a schematic. When you exit the Schematic Editor, these changes are incorporated in the schematic's file and the log file is discarded. When system failures interrupt the program, the log file is not deleted. It can be used to recover from crashes.


Logic Diagram Package - A binder containing detailed logic diagrams of programmable logic devices.  This package is provided with your ABEL software.  Pins, nodes and chip diagrams are also available in ABEL Help by selecting Help: Devices.


Master Symbol - A special symbol that has no electrical significance, but that can be used on a schematic sheet for documentation purposes (for example, a title block or revision block).  The location of a master symbol is fixed relative to one of the corners of the sheet.


Mealy State Machine - A state machine in which the output depends on both the current state and the current input(s).


Miser Bits - Fuses in certain devices that cause the device to operate in a power-saving mode.


Moore State Machine - A state machine in which the output depends only on the current state.


Net - Short for "network". A wire or bus connecting two or more points. All nets are named. If you don't name a net, the program automatically supplies a default name when you save the schematic.


Net Name - An identifier given to a net. If you don't name a net, the program automatically supplies a default name when you save the schematic.


Normalization - The adjustment of a signal's polarity to equal the polarity observed at a given point in the circuit. Normalization of polarity allows designs to be described in device-indepent terms, since the design can be described in terms of logic values observed on a device's outputs, rather than in terms of the device's internal circuitry.


Normalized - A  normalized register feedback signal is an internal feedback signal that has been matched to the signal level measured at the corresponding output pin.


OPEN-ABEL - A feature of ABEL that allows device vendors to provide specialized tools (typically device fitters) that interface directly to ABEL.


Operator - A source file element used in an expression to combine, compare or perform a mathematical function on the identifiers in the expression.  For example, the operator + adds identifiers, and the operator & performs a logical AND function.


Operand - What is operated on by a logical, arithmetic, relational or assignment operator in ABEL-HDL (such as &, +, == and :=).


Ordered Bus - An ordered bus has a name consisting of the individual signal names, separated with commas. (Spaces are not allowed.) For example, CLK,RST,CLR is an ordered bus of the clock, reset, and clear signals.

An ordered bus can also be an indexed array of related signals. For example, D[0-7] represents eight data lines, numbered 0–7.


Overlapping Condition - A condition in which an output has been defined with multiple output values for the same input condition. Overlapping logic can result from incorrectly specified state machine transitions, or from incorrectly specified truth table entries.


PAL - Programmable Array Logic.  PAL is a trademark of AMD, Inc.


Pin - The electrical connection to a symbol in a schematic, or the electrical connection to a net within the symbol.


Pin-to-Pin - A design description that describes the desired functions in terms of input and output pins, leaving the internal device functions unspecified.  This type of design is architecture-independent.


PLA File - An intermediate file created during compilation of ABEL-HDL modules, used to simulate equations, select a device, fit a design into a device, and used to create the programming file.


PLD - Programmable Logic Device. The name is most-often given to devices with a sum-of-products architecture.


Polarity - The polarity of pin and bus markers can be "in", "out", or "bi-directional". An "in" marker has its pointed end facing the device. A "out" marker points away from the device. A "bi-directional" marker is pointed at both ends.


Process - A step in the processing of a source or project.


Programmer Load File - A file that can be used by a programmer to burn parts.  It contains fuse states and possibly test vectors.  A JEDEC file is an example of a programmer load file.


Programmable Output Inversion - A device has programmable output inversion when there is a selectable inverted located between the output pin and the associated flip-flop (if any). Programmable Output Inversion allows flip-flop reset and preset behavior to be reversed, and can also be used to emulate logic array programmable polarity.


Programmable-polarity - Polarity that can be programmed either active high or active low.  Programmable polarity is distinct from programmable output inversion.


Project - A design consisting of sources, including behavioral and schematic logic descriptions, test fixtures, device family, and design documentation.


Properties - Options that control how a source or project is processed.  Edit properties by selecting the process you want to control and clicking on the Properties button.


Q Feedback - The alternative to normalized internal register feedback is Q-feedback, which has the same signal level as the Q-output of the register.    When using ISTYPE 'REG_D,BUFFER', the Q-output of the register and the corresponding pin are at the same signal level.  On the other hand, when using ISTYPE 'REG_D,INVERT', the Q-output of the register is the complement of the pin.


Scalar Net - A net with only one signal.


Sheet - A schematic can consist of more than one sheet. In the Schematic Editor, sheets have the same standard sizes as physical sheets. Wires and buses on different sheets are implicitly connected if they have the same name.


Signal - A single wire (as opposed to a bus) is called a signal.


Signal Attributes - Signal attributes are used to specify architecture-related constraints for signals used in the design.  Attributes are usually applied to signals that are used as outputs.


Simple Net Name - A net name that contains only one signal name.


Source - In The Project Navigator, a Source refers to any design file that is included in the project. Sources appear in the Sources window, and may include schematics, HDL files, test fixtures, and other design documentation. Two special types of Sources, the device and project notebook, appear in every Project Navigator project. The Import feature can be used to add other types of sources (such as documents) to the project.


Special Constants - Constants with specific values in ABEL-HDL, such as .C., .D., and .Z.  Choose Constants from Help: Language Reference for more information.


Spike - A spike is a transient pulse on the inputs of gates, where the duration of the pulse is less than the propagation delay of the gate, so the pulse is not normally propagated to the outputs.


State Machine - A circuit that has memory and feedback. State machines can be described using ABEL-HDL, schematics, or any other form of entry that supports the description of registered designs.


Structural Description - A circuit description in terms of the interconnection of standard components, as in a schematic.


String - A string is a sequence of one or more characters surrounded by ' (single-quotes) or ` (back-quotes).


Strategy - A set of options (properties) associated with a source that affect how that source is processed.  Since strategies contain properties for every processing step, the same strategy can be associated with any part of a project.


Symbol - The essential building block of a schematic.  Symbols may represent other, lower-level schematics or ABEL-HDL modules.


Target Device - The device in which  you intend to implement your design.


Table - A list of values that can be displayed in a schematic that derived attributes.


Transcript - An ongoing status of the operations being performed.


Trigger - A user-defined logic event. The simulation pauses when a specific set of logic conditions, at any number of circuit nodes, occurs.


Turbo Bits - Fuses in certain devices that can be set to make the device operate in a faster, higher-power mode.  Turbo bits are in devices such as the EO310, EO320, EO600, EO900 and E1800.


Unordered Bus - An unnamed wire that has named bus taps attached to it.  An unordered bus is used to clean up a schematic by grouping unrelated signals.  It cannot attach to a bus pin because the signals have no sequence.


User Electronic Signature Word - An identifying string you can program into fuses on some devices.


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