@INPROCEEDINGS{8050802,
author={A. Yousefzadeh and M. Jabłoński and T. Iakymchuk and A. Linares-Barranco and A. Rosado and L. A. Plana and T. Serrano-Gotarredona and S. Furber and B. Linares-Barranco},
booktitle={2017 IEEE International Symposium on Circuits and Systems (ISCAS)},
title={Multiplexing AER asynchronous channels over LVDS links with flow-control and clock-correction for scalable neuromorphic systems},
year={2017},
volume={},
number={},
pages={1-4},
keywords={asynchronous circuits;field programmable gate arrays;flow control;logic testing;LVDS links;address-event-representation;bidirectional SATA connectors;byte alignment techniques;clock correction;clock-correction;flow control;flow-control;handshaking signals;low voltage differential signaling;multiplexing AER asynchronous channels;request and acknowledge;scalable neuromorphic systems;Clocks;Field programmable gate arrays;Multiplexing;Neuromorphics;Receivers;Transmitters;Wires;AER (Address Event Representation);Neuromorphic System;Scalable Neuromoriphic;Virtual Wiring},
doi={10.1109/ISCAS.2017.8050802},
ISSN={2379-447X},
month={May},}