@Article{electronics8010094,
AUTHOR = {Abbaszadeh, Asgar and Iakymchuk, Taras and Bataller-Mompeán, Manuel and Francés-Villora, Jose V. and Rosado-Muñoz, Alfredo},
TITLE = {AnScalable Matrix Computing Unit Architecture for FPGA, and SCUMO User Design Interface},
JOURNAL = {Electronics},
VOLUME = {8},
YEAR = {2019},
NUMBER = {1},
ARTICLE-NUMBER = {94},
URL = {http://www.mdpi.com/2079-9292/8/1/94},
ISSN = {2079-9292},
ABSTRACT = {High dimensional matrix algebra is essential in numerous signal processing and machine learning algorithms. This work describes a scalable square matrix-computing unit designed on the basis of circulant matrices. It optimizes data flow for the computation of any sequence of matrix operations removing the need for data movement for intermediate results, together with the individual matrix operations’ performance in direct or transposed form (the transpose matrix operation only requires a data addressing modification). The allowed matrix operations are: matrix-by-matrix addition, subtraction, dot product and multiplication, matrix-by-vector multiplication, and matrix by scalar multiplication. The proposed architecture is fully scalable with the maximum matrix dimension limited by the available resources. In addition, a design environment is also developed, permitting assistance, through a friendly interface, from the customization of the hardware computing unit to the generation of the final synthesizable IP core. For N x N matrices, the architecture requires N ALU-RAM blocks and performs O( N 2 ), requiring N 2 + 7 and N + 7 clock cycles for matrix-matrix and matrix-vector operations, respectively. For the tested Virtex7 FPGA device, the computation for 500 x 500 matrices allows a maximum clock frequency of 346 MHz, achieving an overall performance of 173 GOPS. This architecture shows higher performance than other state-of-the-art matrix computing units.},
DOI = {10.3390/electronics8010094}
}