Speaker: Gustavo Sutter

Room: 3.0.1

Time: 15:30

Description

Hardware solution for computational problems has obvious and undeniable benefits in speed and power usage regarding to microprocessors based solution. High development costs and solution reuse difficulty are the inconvenients of this strategy. A very used alternative in high performances computation is the use of Reconfigurable Hardware (FPGAs) that allows efficiency and consumption as the hardware with the option to be reprogrammed. The problem is still the high cost in the development of the traditional design flow based in HDLs (Hardware Description Languages). Fortunately, in the last years, the high standard synthesis tools (HLS - High Level Synthesis) allow to describe circuits from C/C++ descriptions or other high level languages.

In this talk, concepts as the high standard synthesis tools from Vivado-HLS (FPGAs Xilinx maker) point of view will be introduced.  After an introduction, a test is conducted to visualize the benefits and design flow.

Gustavo Sutter, Doctorate from Universidad Autónoma de Madrid, Systen Engineer in National University of Central Buenos Aires. He has more than 15 years of experience in FPGA based systems design.   He is specialised in computer architecture area, digital designs, computer arithmetic and high performance computations. He has contributed in numerous national and european research projects and companies transference. He is the author of three books and more than one hundred technical communications. He has given courses in different universities and participates actively in companies training. Currently he is professor and researcher in Escuela Politécnica Superior de la Universidad Autónoma de Madrid and coordinates work in ElectraTraining for the training and transfer in  embedded systems, design of PCBs and FPGAs.