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Conference: ESD Protection Designs for Integrated Circuits

  • May 20th, 2019
Conference: ESD Protection Designs for Integrated Circuits

Speaker: Prof. Albert Wang

Dept. of ECE, University of California, Riverside

Date: Wednesday22 May 15:00 h. (Classroom 3.3.1)

Electrostatic discharge (ESD) failure is the most devastating IC reliability problem. As semiconductor technologies continue to advance to nano nodes, meanwhile ICs become more complex, on-chip ESD protection design emerges as a major IC design challenge, particularly for broad-band RF and high-speed ICs. This lecture discusses advanced on-chip ESD protection design techniques for ICs, including ESD protection fundamentals, mixed-mode ESD simulation-design methodologies, advanced ESD designs for RF and high-speed ICs, and ESD-IC co-design techniques. Real-world ESD protection design examples will be presented.