This Course of Vivado-HLS (Xilinx-FPGAs) consists of three introductory parts and will be held at the School of Engineering of the Universitat de València (ETSE-UV). This Course is organised by Electratraining (Xilinx-ATP) in collaboration with the Communications and Digital Systems Design Group (DSDC) of the Universitat.

The Course is focused on the design of digital circuits that want to use high-level synthesis. Digital design has evolved from hardware description languages (HDL) to high level languages (HLL).

The strategies for using synthesis tools for obtaining efficient digital design from C/C++ descriptions will be taught in this course. There will be learnt concepts of area and speed optimization in the context of high-level synthesis. The generation of IP-cores as well as co-processors of embedded systems as stand-alone systems.

Dates:

Thursday 10 and Friday 11 November 2016 from 09:00 to 18:00.

ETSE-UV Boardroom (0.2.4).

Contact:

José Torres (jose.torres@uv.es)