The TAPEC group researches on hardware devices and architectures for computer perception, with a special focus on image processing and vision devices. In the field of perception architectures, research is carried out on the use of FPGAs for image and visual event processing. In recent years, architectures have been developed that work with pixel or event streams instead of typical image processing.
The most active field of research at present is the design and fabrication of event-driven vision cameras. The TAPEC group has developed a proprietary chip, in CMOS technology, that sends the pixel that has changed the most since it was last read, instead of sending the pixels in order as in conventional images. This technique has advantages such as selective reduction of the information to be processed, simple and synchronous interface, high processing speed and motion analysis, etc. As an example, the latest camera developed is capable of tracking objects with a temporal resolution of microseconds; to achieve the same with a conventional camera, it would have to operate at a rate of 500,000 images per second, with hardware capable of processing all that information in real time, which is not feasible today.
- Realise change-guided selective vision sensors.
- Develop architectures for processing pixel streams for motion analysis.
- Specific architectures and FPGAs
Design of application-specific architectures using FPGA. Specific computer vision architectures.
- Robotics and control
Design of robots, vehicles, sensorisation. Design of closed-loop control architectures.
- CMOS vision sensors
Design of integrated circuits for vision, especially application-specific selective gear-guided vision and cameras.
- BOLUDA GRAU, JOSE ANTONIO
- PDI-Titular d'Universitat
- Coordinador/a de Mobilitat
- Coordinador/a Curs
- ContraerExpandirPARDO CARPIO, FERNANDOPDI-Catedratic/a d'Universitat
Càndid Reig; María-Dolores Cubells-Beltrán; Fernando Pardo; Francisco Vegara; José-Antonio Boluda; Sofia Abrunhosa; Susana Cardoso(2023)Research Group on Technologies and Architectures for Machine PerceptionAip Advances, 13(2), pp. 025225 - 5. ISSN: 2158-3226
F. Pardo; C. Reig; J.A. Boluda; F. Vegara(2019)Research Group on Technologies and Architectures for Machine PerceptionSensors, 19(2), p. 437. ISSN: 1424-8220
Boluda Grau, José A.; Pardo Carpio, Fernando; Vegara Meseguer, Francisco(2016)Research Group on Technologies and Architectures for Machine PerceptionSensors, 16(11), pp. 1875-1 - 1875-19. ISSN: 1424-8220
Fernando Pardo; Jose A. Boluda; Francisco Vegara(2015)Research Group on Technologies and Architectures for Machine PerceptionSolid-State Electronics, 114, pp. 111 - 114. ISSN: 0038-1101
Fernando Pardo; Jose A. Boluda; Francisco Vegara(2015)Research Group on Technologies and Architectures for Machine PerceptionIEEE Journal of Solid-State Circuits, 50(3), pp. 786 - 798. ISSN: 0018-9200
Vegara Meseguer, Francisco; Zuccarello, Pedro; Boluda Grau, José A.; Pardo Carpio, Fernando(2013)Research Group on Technologies and Architectures for Machine PerceptionSensors, 13(10), pp. 13143 - 13162. ISSN: 1424-8220
Jose A. Boluda; Pedro Zuccarello; Fernando Pardo; Francisco Vegara(2011)Research Group on Technologies and Architectures for Machine PerceptionSensors, 11(11), pp. 11000 - 11020. ISSN: 1424-8220
Fernando Pardo; Pedro Zuccarello; Jose A. Boluda; Francisco Vegara(2011)Research Group on Technologies and Architectures for Machine PerceptionIEEE Transactions on Circuits and Systems for Video Technology, 21(10), pp. 1415 - 1423. ISSN: 1051-8215
P.Zuccarello; F.Pardo; A.de la Plaza; J.A.Boluda(2010)32x32 winner-take-all matrix with single winner selection.Electronics Letters, 46(5), pp. 333 - 335. ISSN: 0013-5194
Jose A. Boluda; Francisco Vegara; Fernando Pardo; Pedro Zuccarello(2009)Research Group on Technologies and Architectures for Machine PerceptionLecture Notes in Computer Science, 5856, pp. 37 - 44. ISSN: 0302-9743
Fernando Pardo; Jose A. Boluda(2009)Research Group on Technologies and Architectures for Machine PerceptionComputers & Electrical Engineering, 35(5), pp. 803 - 814. ISSN: 0045-7906
Fernando Pardo, Jose A. Boluda, Francisco Vegara, Pedro Zuccarello(2008)On the Advantages of Asynchronous Pixel Reading and Processing for High-Speed Motion Estimation.Lecture Notes in Computer Science, 5358, pp. 205 - 215. ISSN: 0302-9743
Boluda J. A.; Pardo F.(2007)Research Group on Technologies and Architectures for Machine PerceptionLecture Notes in Computer Science, 4673, pp. 77 - 85. ISSN: 0302-9743
Sosa J. C.; Boluda J. A.; Pardo F.; Gómez-Fabela R.(2007)Research Group on Technologies and Architectures for Machine PerceptionJournal Of Real-Time Image Processing, 2(4), pp. 259 - 270. ISSN: 1861-8200
Pardo F.; Boluda J. A.; De Ves E.(2004)Feature extraction and correlation for time-to-impact segmentation using log-polar images.Lecture Notes in Computer Science, 3046, pp. 887 - 895. ISSN: 0302-9743
Boluda J. A.; Pardo F.(2003)A reconfigurable architecture for autonomous visual navigation.Machine Vision and Applications, 13(5-6), pp. 322 - 331. ISSN: 0932-8092
Boluda J. A.; Pardo F.(2003)Synthesizing on a reconfigurable chip an autonomous robot image processing system.Lecture Notes in Computer Science, 2778, pp. 458 - 467. ISSN: 0302-9743
Pardo F.; Boluda J. A.; Coma I.; Micó F.(2002)High speed log-polar time to crash calculation for mobile vehicles.Image processing and communications, 8(2), pp. 23 - 32. ISSN: 1425-140X
F. Pardo; B. Dierickx; D. Scheffer(1998)Space-Variant Non-Orthogonal Structure CMOS Image Sensor Design.IEEE Journal of Solid-State Circuits, 33(6), pp. 842 - 849. ISSN: 0018-9200
F. Pardo; B. Dierickx; D. Scheffer(1997)CMOS Foveated Image Sensor: Signal Scaling and Small Geometry Effects.IEEE Transactions on Electron Devices, 44(10), pp. 1731 - 1737. ISSN: 0018-9383
Boluda J. A.; Domingo J.; Pardo F.; Pelechano J.(1997)Detecting motion independent of the camera movement through a log-polar differential approach.Lecture Notes in Computer Science, 1296, pp. 702 - 709. ISSN: 0302-9743
Boluda J. A.; Pardo F.;(1996)Tecnología y fabricación de circuitos integrados. Cómo se hace un chip I.Jumping(12), pp. 30 - 35. ISSN: 2530-8785
Boluda J. A.; Pardo F.;(1996)Tecnología y fabricación de circuitos integrados. Cómo se hace un chip II.Jumping(13), pp. 38 - 41. ISSN: 2530-8785
Boluda J. A.; Pardo F.;(1996)Fallos en sistemas informáticos.Jumping(8), pp. 32 - 34. ISSN: 2530-8785
Felici S.; Pérez J. J.; Pardo F.;Boluda J. A.;(1996)Evolución de la arquitectura PC en Backplane.Mundo Electrónico(266), pp. 56 - 63. ISSN: 0300-3787
Pardo F.; Boluda J. A.; Martínez R. J.; Pérez C.;(1994)Futurebus+: Aplicación en sistemas tolerantes a fallos.Mundo Electrónico(246), pp. 44 - 49. ISSN: 0300-3787
Pardo F.; Boluda J. A.; Martínez R. J.; Pérez C.;(1994)Lógica programable: Criterios de selección.Mundo Electrónico(249), pp. 27 - 31. ISSN: 0300-3787
Journal Publications
Jose A. Boluda; Pedro Zuccarello; Fernando Pardo; Francisco Vegara,(2012).On the Design of Change-driven Data-flow Algorithms and Architectures for High-speed Motion Analysis.Proceedings of the 9th International Conference on Informatics in Control, Automation and Robotics, ICINCO 2012... Volume. 1 . (pp. 548 - 553)..
Pardo F.; Boluda J. A.;,(2011).VHDL: Lenguaje para síntesis y modelado de circuitos. Tercera Edición... (pp. 1 - 308)..
Fernando Pardo; Jose A. Boluda,(2011).VHDL: Lenguaje para síntesis y modelado de circuitos. Tercera Edición Iberoamericana... (pp. 1 - 308)..
Jose A. Boluda; Fernando Pardo,(2004).Tecnología y Diseño de Sistemas Digitales... (pp. 1 - 168)..
Pardo F.; Boluda J. A.;,(2003).VHDL: Lenguaje para síntesis y modelado de circuitos. Segunda Edición... (pp. 1 - 272)..
Fernando Pardo; Jose A. Boluda,(2000).VHDL: Lenguaje para síntesis y modelado de circuitos. Edición Iberoamericana... (pp. 1 - 256)..
Fernando Pardo; Jose A. Boluda,(1999).VHDL: Lenguaje para síntesis y modelado de circuitos. Primera Edición... (pp. 1 - 256)..
Other publications
- ContraerExpandirBOLUDA GRAU, JOSE ANTONIOPDI-Titular d'UniversitatCoordinador/a de MobilitatCoordinador/a Curs
Càndid Reig; María-Dolores Cubells-Beltrán; Fernando Pardo; Francisco Vegara; José-Antonio Boluda; Sofia Abrunhosa; Susana Cardoso(2023)Research Group on Technologies and Architectures for Machine PerceptionAip Advances, 13(2), pp. 025225 - 5. ISSN: 2158-3226
F. Pardo; C. Reig; J.A. Boluda; F. Vegara(2019)Research Group on Technologies and Architectures for Machine PerceptionSensors, 19(2), p. 437. ISSN: 1424-8220
Boluda Grau, José A.; Pardo Carpio, Fernando; Vegara Meseguer, Francisco(2016)Research Group on Technologies and Architectures for Machine PerceptionSensors, 16(11), pp. 1875-1 - 1875-19. ISSN: 1424-8220
Fernando Pardo; Jose A. Boluda; Francisco Vegara(2015)Research Group on Technologies and Architectures for Machine PerceptionIEEE Journal of Solid-State Circuits, 50(3), pp. 786 - 798. ISSN: 0018-9200
Fernando Pardo; Jose A. Boluda; Francisco Vegara(2015)Research Group on Technologies and Architectures for Machine PerceptionSolid-State Electronics, 114, pp. 111 - 114. ISSN: 0038-1101
Vegara Meseguer, Francisco; Zuccarello, Pedro; Boluda Grau, José A.; Pardo Carpio, Fernando(2013)Research Group on Technologies and Architectures for Machine PerceptionSensors, 13(10), pp. 13143 - 13162. ISSN: 1424-8220
Jose A. Boluda; Pedro Zuccarello; Fernando Pardo; Francisco Vegara(2011)Research Group on Technologies and Architectures for Machine PerceptionSensors, 11(11), pp. 11000 - 11020. ISSN: 1424-8220
Fernando Pardo; Pedro Zuccarello; Jose A. Boluda; Francisco Vegara(2011)Research Group on Technologies and Architectures for Machine PerceptionIEEE Transactions on Circuits and Systems for Video Technology, 21(10), pp. 1415 - 1423. ISSN: 1051-8215
P.Zuccarello; F.Pardo; A.de la Plaza; J.A.Boluda(2010)32x32 winner-take-all matrix with single winner selection.Electronics Letters, 46(5), pp. 333 - 335. ISSN: 0013-5194
Jose A. Boluda; Francisco Vegara; Fernando Pardo; Pedro Zuccarello(2009)Research Group on Technologies and Architectures for Machine PerceptionLecture Notes in Computer Science, 5856, pp. 37 - 44. ISSN: 0302-9743
Fernando Pardo; Jose A. Boluda(2009)Research Group on Technologies and Architectures for Machine PerceptionComputers & Electrical Engineering, 35(5), pp. 803 - 814. ISSN: 0045-7906
Fernando Pardo, Jose A. Boluda, Francisco Vegara, Pedro Zuccarello(2008)On the Advantages of Asynchronous Pixel Reading and Processing for High-Speed Motion Estimation.Lecture Notes in Computer Science, 5358, pp. 205 - 215. ISSN: 0302-9743
Boluda J. A.; Pardo F.(2007)Research Group on Technologies and Architectures for Machine PerceptionLecture Notes in Computer Science, 4673, pp. 77 - 85. ISSN: 0302-9743
Sosa J. C.; Boluda J. A.; Pardo F.; Gómez-Fabela R.(2007)Research Group on Technologies and Architectures for Machine PerceptionJournal Of Real-Time Image Processing, 2(4), pp. 259 - 270. ISSN: 1861-8200
Pardo F.; Boluda J. A.; De Ves E.(2004)Feature extraction and correlation for time-to-impact segmentation using log-polar images.Lecture Notes in Computer Science, 3046, pp. 887 - 895. ISSN: 0302-9743
Boluda J. A.; Pardo F.(2003)A reconfigurable architecture for autonomous visual navigation.Machine Vision and Applications, 13(5-6), pp. 322 - 331. ISSN: 0932-8092
Boluda J. A.; Pardo F.(2003)Synthesizing on a reconfigurable chip an autonomous robot image processing system.Lecture Notes in Computer Science, 2778, pp. 458 - 467. ISSN: 0302-9743
Pardo F.; Boluda J. A.; Coma I.; Micó F.(2002)High speed log-polar time to crash calculation for mobile vehicles.Image processing and communications, 8(2), pp. 23 - 32. ISSN: 1425-140X
Boluda J. A.; Domingo J.(2001)On the advantages of combining differential algorithms, pipelined architectures and log-polar vision for detection of self-motion from a mobile robot.Robotics and Autonomous Systems, 37(4), pp. 283 - 296. ISSN: 0921-8890
Boluda J. A.; Blasco F.; Pardo F.: Pelechano J.(1999)A pipelined reconfigurable architecture for visual-based navigation.Euromicro, 1, pp. 71 - 74
Boluda J. A.; Domingo J.; Pardo F.; Pelechano J.(1997)Detecting motion independent of the camera movement through a log-polar differential approach.Lecture Notes in Computer Science, 1296, pp. 702 - 709. ISSN: 0302-9743
Felici S.; Pérez J. J.; Pardo F.;Boluda J. A.;(1996)Evolución de la arquitectura PC en Backplane.Mundo Electrónico(266), pp. 56 - 63. ISSN: 0300-3787
Boluda J. A.; Pardo F.;(1996)Tecnología y fabricación de circuitos integrados. Cómo se hace un chip I.Jumping(12), pp. 30 - 35. ISSN: 2530-8785
Boluda J. A.; Pardo F.;(1996)Tecnología y fabricación de circuitos integrados. Cómo se hace un chip II.Jumping(13), pp. 38 - 41. ISSN: 2530-8785
Boluda J. A.; Pardo F.;(1996)Fallos en sistemas informáticos.Jumping(8), pp. 32 - 34. ISSN: 2530-8785
Pardo F.; Boluda J. A.; Martínez R. J.; Pérez C.;(1994)Futurebus+: Aplicación en sistemas tolerantes a fallos.Mundo Electrónico(246), pp. 44 - 49. ISSN: 0300-3787
Pardo F.; Boluda J. A.; Martínez R. J.; Pérez C.;(1994)Lógica programable: Criterios de selección.Mundo Electrónico(249), pp. 27 - 31. ISSN: 0300-3787
Journal Publications
Jose A. Boluda; Pedro Zuccarello; Fernando Pardo; Francisco Vegara,(2012).On the Design of Change-driven Data-flow Algorithms and Architectures for High-speed Motion Analysis.Proceedings of the 9th International Conference on Informatics in Control, Automation and Robotics, ICINCO 2012... Volume. 1 . (pp. 548 - 553)..
Jose A. Boluda; Pedro Zuccarello; Fernando Pardo; Francisco Vegara,(2012).On the Design of Change-driven Data-flow Algorithms and Architectures for High-speed Motion Analysis.Proceedings of the 9th International Conference on Informatics in Control, Automation and Robotics, ICINCO 2012... Volume. 1 . (pp. 548 - 553)..
Pardo F.; Boluda J. A.;,(2011).VHDL: Lenguaje para síntesis y modelado de circuitos... (pp. 1 - 308)..
Fernando Pardo; Jose A. Boluda,(2011).VHDL: Lenguaje para síntesis y modelado de circuitos. Tercera Edición Iberoamericana... (pp. 1 - 308)..
Francisco Vegara; Jose A. Boluda; Juan Domingo; Fernando Pardo; Xaro Benavent,(2009).Accelerating Motion Analysis Algorithms with a Pixel Change-Driven Scheme.The 2009 International Conference on Image Processing, Computer Vision, and Pattern Recognition 2009... (pp. 895 - 900)..
Pardo F.; Boluda J. A.; Benavent X.; Domingo J.; Sosa J. C.,(2005).Circle detection and tracking speed-up based on change-driven image processing.ICGST International Conference on Graphics, Vision and Image Processing... (pp. 1 - 6)..
Boluda J. A.; Pardo F.;,(2005).La enseñanza de Periféricos con VHDL y lógica programable.V Jornadas de Computación Reconfigurable y Aplicaciones.. (pp. 383 - 386)..
Boluda J. A.; Pardo F.,(2004).Tecnología y diseño de sistemas digitales... (pp. 1 - 182)..
Boluda J. A.; Pardo F.;,(2004).Space-Variant image processing: Taking advantage of data reduction and polar coordinates.SPIE's International Technical Group Newsletter. Special Issue on Smart Image Acquisition Processing... Volume. 14 . Number. 1 . (pp. 10 - 12)..
Pardo F.; Boluda J. A.;,(2004).SimuRed: Un simulador de redes de multicomputadores interactivo y visual.Computación de Altas Prestaciones. XV Jornadas de Paralelismo... (pp. 351 - 355)..
Sosa J. C.; Pardo F.; Boluda J. A.; Gómez R.;,(2004).Desarrollo de una interfaz PCI para un sistema de visión en una FPGA.FPGAs: Computación y Aplicaciones.. (pp. 531 - 540)..
Sosa J. C.; Gómez R.; Pardo F.; Boluda J.A.;,(2004).Vision log-polar basada en una FPGA y el bus PCI para aplicaciones en tiempo-real.Encuentro Internacional de Ciencias de la Computación. Congreso Internacional de Cómputo Reconfigurable y FPGAs... (pp. 210 - 219)..
Pardo F.; Boluda J. A.;,(2003).VHDL: Lenguaje para síntesis y modelado de circuitos. 2ª Edición actualizada... (pp. 1 - 251)..
Pardo F.; Boluda J. A.; Sosa J. C.,(2003).A log-polar image processing system on a chip.Proceedings of the XVIII Conference on Design of Circuits and Integrated Systems... (pp. 449 - 454)..
Pardo F.; Boluda J. A.;,(2003).Tarjeta de desarrollo para el laboratorio de microcontroladores PIC.XIV Jornadas de Paralelismo.. (pp. 287 - 296)..
Pardo F.; Boluda J. A.; Sosa J. C.,(2003).Transformación Log-Polar en FPGAs Utilizando CORDIC.Computación reconfigurable & FPGAS.. (pp. 99 - 106)..
Sosa J. C.; Pardo F.; Boluda J. A.;,(2003).Implementación de un control neuronal en una FPGA y su comparación con otras técnicas de control.Computación reconfigurable & FPGAS.. (pp. 309 - 316)..
Pardo F.; Boluda J.A.; de Ves E.;,(2002).Development Board for the Microcontroller Lab.TELEC'02 International Conference.. (pp. 1 - 4)..
de Ves E.; Pardo F.; Boluda J.A.;,(2002).High-speed movement analysis from log-polar images using dynamic feature extraction and correlation.TELEC'02 International Conference.. (pp. 1 - 4)..
Boluda J.A.; Pardo F.; de Ves E.;,(2002).Estimating Time-to-impact Data with an Autonomous Vehicle Portable Pipelined Architecture.TELEC'02 International Conference.. (pp. 1 - 4)..
Martínez R. J.; Boluda J. A.; Pérez J. J.,(2001).Estructura de Computadores y Periféricos... (pp. 1 - 374)..
Coma I; Pardo F.; Boluda J.A.; Mico F.;,(2001).Virtual-reality environment for 3D scene recosntruction from time to impact lof-polar images.SERVICEROB Proceedings.. (pp. 75 - 80)..
Boluda J. A.; Pardo F.; Micó F.;,(2001).Arquitecturas reconfigurables de procesamiento de imágenes para la navegación de robots autónomos.I Jornadas de Computación Reconfigurable y Aplicaciones... (pp. 166 - 173)..
Martínez R. J.; Boluda J. A.; Pérez J. J.,(2001).Estructura de Computadores y Periféricos... (pp. 1 - 374)..
Pardo F.; Llorens I.; Micó F.; Boluda J. A.,(2000).Space variant vision and pipelined architecture for time to impact computation.Proceedings of the International Workshop on Computer Architectures for Machine Perception.. (pp. 122 - 126)..
Boluda J. A.; Domingo J.; Pardo F.; Pelechano J.,(2000).FPGA implementation of a log-polar motion detection algorithm.Intelligent Autonomous Systems 6.. (pp. 851 - 858)..
Pardo F.; Boluda J. A.;,(2000).VHDL: Lenguaje para síntesis y modelado de circuitos... (pp. 1 - 238)..
Pardo F.; Boluda J. A.;,(1999).VHDL: Lenguaje para síntesis y modelado de circuitos... (pp. 1 - 238)..
Boluda J. A.; Pardo F.; Blasco F.;,(1999).A scalable reconfigurable FPGA based architecture for robotic navigation.Proceedings of XIV Design of Circuits and Integrated Systems Conference.. (pp. 831 - 836)..
Blasco F.; Pardo F.; Boluda J. A.;,(1999).A FPGA based PCI bus interface for a real-time log-polar image processing system.Proceedings of XIV Design of Circuits and Integrated Systems Conference.. (pp. 379 - 384)..
Boluda J. A.; Pardo F.; Pelechano J.;,(1998).Reconfigurable architectures for machine perception. An approach for autonomous vehicle navigation.Workshop on European Scientific and Industrial Collaboration on promoting Adavanced Technologies in Manufacturing.. (pp. 359 - 363)..
Blasco F.; Pardo F.; Boluda J. A.;,(1998).Sistema de adquisición de imágenes log-polares con alta velocidad basada en bus PCI.XIX Jornadas de Automática.. (pp. 277 - 280)..
Boluda J. A.; Pardo F.; Blasco F.; Pelechano J.;,(1998).Una arquitectura segmentada para el cálculo del tiempo al impacto con visión log-polar.XIX Jornadas de Automática.. (pp. 281 - 285)..
Boluda J. A.; Domingo J.; Pardo F.; Pelechano J.,(1997).Motion detection independent of the camera movement with a log-polar sensor.Proceedings of the 13th International Conference in Digital Signal Processing.. Volume. 2 . (pp. 809 - 812)..
Pardo F.; Boluda J. A.;,(1997).Cámaras CMOS y Visión Foveal.Seminario Anual de Automática, Electrónica Industrial e Instrumentación... (pp. 316 - 321)..
Boluda J. A.; Pardo F.; Kayser T.; Pérez J. J.; Pelechano J.,(1996).A new foveated space-variant camera for robotic applications.Proceedings of the Third IEEE International Conference on Electronics, Circuits and Systems... Volume. 2 . (pp. 680 - 683)..
Pardo F.; Boluda J. A.; Pérez J. J.; Dierickx B.; Scheffer D.,(1996).Design issues on CMOS space-variant image sensors.Advance Focal Plane Arrays and Electronic Cameras.. Volume. 2950 . (pp. 98 - 107)..
Pardo F.; Boluda J. A.; Pérez J. J.; Felici S.; Dierickx B.; Scheffer D.,(1996).Response properties of a foveated space-variant CMOS image sensor.Proceedings of the 1996 IEEE International Symposium on Circuits and Systems... Volume. 1 . (pp. 373 - 376)..
Pardo F.; Boluda J. A.; Pérez J. J.; Felici S,; Dierickx B.,(1996).Design of a foveated log-polar image sensor using standard CMOS technology.Proceedings of the XI Conference on Design of Integrated Circuits and Systems.. (pp. 49 - 54)..
Boluda J. A.; Pérez J. J.; Felici S,; de Ves E.; Pardo F.;,(1996).Proyecto Puente de Lavado: una experiencia de diseño en el marco de colaboración Universidad-Industria.Segundo Workshop Iberchip.. (pp. 69 - 77)..
Boluda J. A.; Pérez J. J.; Felici S,; de Ves E.; Pardo F.; Pelaez S.; Insenser J. M.;,(1996).A custom communications system for I/O control in industrial applications.Proceedings of the XI Conference on Design of Integrated Circuits and Systems.. (pp. 76 - 78)..
Boluda J. A.; Pardo F.; Pérez J. J.; Domingo J.; Pelechano J.,(1996).Seguimiento de objetos mediante una cámara log-polar y visión foveal.XVII Jornadas de Automática... (pp. 79 - 84)..
Martínez R. J.; Pérez C.; Fabregat G.; Boluda J. A.; Pardo F.;,(1995).DPU: a FB+ based fault-tolerant system.Proceedings of Open Bus System 1995: OBS'95... (pp. 229 - 236)..
Pardo F.; Vegara F.; Boluda J. A.; Felici S.;,(1995).Sensores CMOS para robótica e industria: Sensor retínico espacio variante y visión activa.IV Congreso de la Asociación Española de Robótica y Automatización Tecnologías de la Producción.. (pp. 101 - 106)..
Other publications
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