On 18 June at 15:30 in the classroom 2.1.5 the Dr Gustavo Sutter will teach the seminar on circuits of Vivado High-Level Synthesis Languages.

Digital design has evolved from hardware description languages (HDL - such as VHDL or Verilog) to high level languages (HLL). The strategies for using synthesis tools for obtaining efficient digital design from C/C++ descriptions will be taught in this seminar.

As a part of the seminar the scheduling and Binding concepts will be reviewed and the design tool Vivado-HLS will be introduced (previously known as AutoESL).

Through examples the concepts of latency, productiveness, initiation interval: unrolling, loop flattening, segmentation (pipeline) at function and blocks level; concurrent access to repairs.  Finally an IP-core of the example for using it in a Development Board will be carried out.

CV:
Doctor in IT and Telecommunications by the Autonomous University of Madrid, Systems Engineer in the National University of the Center of the Buenos Aires Province (Argentina).

He has over 15 years experience in designing systems based on FPGA. He specialises in the area of architecture of computers, digital designs with FPGA, computer arithmetic and high-performance computations. He has collaborated on many projects of national and European research and transfer projects with companies. He has wrote three books and a hundred technical papers. He has taught dozens of courses at different universities and participates actively in the training to companies.

Currently, he is professor and researcher at the Escuela Politécnica Superior of the Universidad Autónoma of Madrid and coordinates the tasks of ElectraTraining for training and transferring in topics of embedded systems, PCBs and FPGAs design.